Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
32
4.13. PLL Feedback Division Setting Register : CCPLLFBR
(CCtl PLL FB clock division Register)
The bit configuration of the PLL feedback division setting register is shown.
It is a register that sets the multiple ratio of PLL.
This register can be written only at PLL/SSCG clock oscillation stop (CSELR.PCEN = "0").
CCPLLFBR: Address 0525
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
IDIV[6:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7] (Reserved)
[bit6 to bit0] IDIV[6:0] (pll feedback Input DIVider ratio settings) : Setting of PLL macro FB input
dividing frequency ratio
PLL multiple ratio is set.
IDIV[6:0]
Dividing frequency ratio setting
0000000 to
0001011
Setting is prohibited
0001100
13
0001101
14
0001110
15
…
……
1100010
99
1100011
100
1100100 to
1111111
Setting is prohibited
A set value is limited. See "5.1.4 Limitations when PLL/SSCG Clock is used" when you set it.
MB91520 Series
MN705-00010-1v0-E
193