Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
41
4.20. Clock Gear Configuration Setting Register 2 :
CCCGRCR2 (CCtl Clock Gear Config. Register 2)
The bit configuration of the division setting register 0 is shown.
Sets various settings of clock gear.
This register can be written only when PLL/SSCG clock oscillation is stopped. (CSELR.PCEN = "0").
CCCGRCR2 : Address 052F
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
GRLP[7:0]
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to bit0] GRLP[7:0] (clock GeaR LooP number selection) : clock gear loop number selection
These bits select the loop number of one step. The setting enabled number of iteration is between 1 to 256.
Step is incremented/decremented when the number set to this bit is completed.
GRLP[7:0]
Loop number
0000_0000
1
0000_0001
2
0000_0010
3
…
……
1111_1101
254
1111_1110
255
1111_1111
256
MB91520 Series
MN705-00010-1v0-E
202