Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
44
4.22. PMU Clock Division Setting Register 0 : CCPMUCR0
(CCtl PMU Clock division Register 0)
The bit configuration of the division setting register 0 is shown.
This register does the setting of clock dividing frequency of the PMU. .
CCPMUCR0 : Address 0532
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
FST
Reserved
FDIV[1:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit7] FST (F-divider STatus monitor): F-divider status monitor
A time lag by clock switch occurs until FDIV[1:0] register is written and the written value is reflected.
Whether the setting value is reflected can be monitored by this bit.
Normally, it takes RTC clock × about 4 cycles + PCLK1 × about 4 cycles to reflect the setting value of the
register.
FST
Monitor
0
Completion of reflecting the written value
1
During reflecting the written value
[bit6 to bit2] (Reserved)
[bit1, bit0] FDIV[1:0] (F-DIVide ratio setting): F-divide ratio setting
Sets the division rate of F-divider. The clock less than 32kHz must be provided with PMU. When
CCRTSELR:CSC=0 (selection of main clock), this bit is set to be less than 32kHz by F divider.
FDIV[1:0]
Division rate
Target main oscillation frequency
00
Divided by 128 (Initial value)
4MHz
01
Divided by 256
8MHz
10
Divided by 384
12MHz
11
Divided by 512
16MHz
Note:
Writing to this bit is ignored while the CCPMUCR0:FST bit is "1".
When CCRTSELR:CSC=1 (selection of sub oscillation clock), F-division rate become undivided in spite of
the value of this bit.
MB91520 Series
MN705-00010-1v0-E
205