Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
45
4.23. PMU Clock Division Setting Register 1 : CCPMUCR1
(CCtl PMU Clock division Register 1)
The bit configuration of the division setting register 0 is shown.
This register does the setting of clock dividing frequency of the PMU.
CCPMUCR1 : Address 0533
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
GST
Reserved
GDIV[4:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R,WX
R0,WX
R0,WX
R/W
R/W
R/W
R/W
R/W
[bit7] GST (G-divider STatus monitor): G-divider status monitor
A time lag by clock switch occurs until GDIV[4:0] register is written and the written value is reflected.
Whether the setting value is reflected can be monitored by this bit.
Normally, it takes RTC clock × about 4 cycles + PCLK1 × about 4 cycles to reflect the setting value of the
register.
GST
Monitor
0
Completion of reflecting the written value
1
During reflecting the written value
Note:
Writing to CCPMUCR1.GDIV[4:0] is ignored while this bit is "1".
[bit6, bit5] (Reserved)
[bit4 to bit0] GDIV[4:0] (G-DIVide ratio setting) : G-divide ratio setting
These bits set the division rate of G-divider. The period of the PMU clock must be more than four times the
period of the bus clock (APB) which is provided with PMU. The division rate of the PMU clock is set by this
divider to meet the above relation.
GDIV[4:0]
Division rate
00000
No divide (Initial value)
00001
2
00010
3
…
……
11101
30
11110
31
11111
32
MB91520 Series
MN705-00010-1v0-E
206