Fujitsu FR81S User Manual
CHAPTER 8: DMA CONTROLLER (DMAC)
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : DMA CONTROLLER (DMAC)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
38
Figure 5-6 Data Transfer Example If Channel Priority Is Set by Round Robin
Updating of transfer address
The transfer source address and transfer destination address are updated each time data which size has been
set by the DCCRn:TS is transferred. The address updating can be increasing, decreasing, or fixed. When
increasing or decreasing, its address amount is determined by the transfer size (DCCRn:TS). If fixed, the
address value does not change. Table 5-4 shows the address increasing or decreasing width during address
updating. If an overflow occurs due to address updating, the relevant bit is discarded.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
Transfer request is generated
on ch.0, ch.1, ch.3
on ch.0, ch.1, ch.3
ch.0 transfer end
ch.1 transfer end
ch.3 transfer end
ch.0
ch.1
ch.3
Channel priority for each block
(1) ch.0 > ch.1 > ch.2 > ch.3
(2) ch.1 > ch.2 > ch.3 > ch.0
(3) ch.2 > ch.3 > ch.0 > ch.1
(4) ch.2 > ch.0 > ch.1 > ch.3
(5) ch.2 > ch.1 > ch.3 > ch.0
(6) ch.2 > ch.3 > ch.0 > ch.1
(7) ch.2 > ch.0 > ch.1 > ch.3
(8) ch.2 > ch.1 > ch.3 > ch.0
(9) ch.2 > ch.3 > ch.0 > ch.1
(10) ch.2 > ch.0 > ch.1 > ch.3
MB91520 Series
MN705-00010-1v0-E
337