Fujitsu FR81S User Manual

CHAPTER 8: DMA CONTROLLER (DMAC)

5. Operation

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : DMA CONTROLLER (DMAC)

FUJITSU SEMICONDUCTOR CONFIDENTIAL

(A) Multi-function serial interface

If a PE, FRE, or ORE flag is set

(B) LIN-UART

If a PE, FRE, or ORE flag is set

If a transfer stop request is issued, the transfer is suspended after one block of the current data has been

transferred. If the data transfer is suspended, the following occur.

⋅

The SP bit of DMA channel status registers (DCSR0 to DCSR15) is set to "1".

⋅

The CE bit of DMA channel control registers (DCCR0 to DCCR15) is set to "0".

⋅

The already detected transfer request is cleared.

While a transfer stop request being issued, a new transfer request is rejected. Restart the DMA transfer in

the following procedure.

1. Clear the flags described in paragraphs (A) and (B) to make the transfer stop request invalid.

2. Set the SP bit of DMA channel status registers (DCSR0 to DCSR15) of the corresponding channel

to "0".

3. Set the CE bit of DMA channel control registers (DCCR0 to DCCR15) to "1".

4. Issue a new transfer request.

Table 5-6 Settings to Restart the Suspended Data Transfer

DME clear

CE clear

If a transfer stop request from transfer

request source peripheral is detected

Setting to

restart

transfer

(1) Set the DME bit

(1) Set the CE bit

(2) Issue a transfer

request

(1) The transfer request is negated

(2) The SP bit is cleared

(3) The CE bit is set

(4) Issue a transfer request



Transfer termination

Data transfer can terminate normally or abnormally.

•

Normal termination

The transfer terminates normally at the time when the transfers for the number of times set by the transfer

count (DTCRn:DTC) end. When terminated normally, the DCSRn:NC bit of the corresponding channel is

set. Also, the DCCRn:CE bit is cleared and data transfer is stopped. However, if the reloading of the

transfer count has been set by non-software transfer request source, the DCCRn:CE bit of the channel is

not cleared.

If the transfer count (DTCRn:DTC ) is "0" and if the DCCRn:CE bit of the corresponding channel is set

to "1", the DCSRn:NC bit is set in the similar way as for the normal termination. Before setting the

DCCRn:CE bit to "1", be sure to set the DTCRn:DTC bit to "1" or a larger value.

•

Abnormal termination

If an inhibited value is set in the register, data transfer terminates abnormally. When terminated

abnormally, the DCSRn:AC bit of the corresponding channel is set. Also, the DCCRn:CE bit is cleared

and data transfer is stopped.

The items not allowed to set to registers are listed below.

⋅

Transfer mode

: DCCRn:TM = 10

⋅

Transfer source address count

: DCCRn:SAC = 10

⋅

Transfer destination address count

: DCCRn:DAC = 10

MB91520 Series

MN705-00010-1v0-E

341