Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
18
4.9. DMA Request Clear Register 9 : ICSEL9 (Interrupt
Clear SELect register 9)
The bit configuration of DMA request clear register 9 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #43).
ICSEL9: Address 0409
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
PPGSEL3[1:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX
R/W
R/W
[bit1, bit0] PPGSEL3[1:0] (PPG SELection3) : Interrupt clear selection bits for PPG6, 7, 16, 17
PPGSEL3[1:0]
Clear target
00
PPG6
01
PPG7
10
PPG16
11
PPG17
MB91520 Series
MN705-00010-1v0-E
363