Fujitsu FR81S User Manual
CHAPTER 11: I/O PORTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : I/O PORTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
13
4.5. Port Pull-up/down Enable Register 00 to 19 : PPER00
to 19 (Port Pull-up/down Enable Register 00 to 19)
The bit configuration of port pull-up/down enable register 00 to 19 is shown below.
These registers are used to enable pull-up or pull-down each port. These registers are functioned for input
condition pins only. PPFER00 to PPER19 are key code target registers.
PPER00 to PPER19 : Address 0EC0
H
, 0EC1
H
,
(Access : Byte, Half-word,
Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
P[7:0]
Initial
value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to bit0] P (Port) : Pull-up/down enable selection bits
PPER0.P[7:0] is for external pins P007 to P000
PPER1.P[7:0] is for external pins P017 to P010
PPER2.P[7:0] is for external pins P027 to P020
(A similar process continues)
The assignment is as shown above.
P[n]
Operation
0
Pull-up/down disabled (Initial value)
1
Pull-up/down enabled
See "List of Pin Functions" and " I/O Circuit Types" of "CHAPTER: OVERVIEW" for the presence of
pull-up/pull-down of each port.
PPER13.P7, PPER14.P[7:5, 1:0], PPER15.P[7:6] are reserved bits. Both writing to and reading from these
bits have no effect.
PPER13.P[6:5] are reserved bits in the dual clock products. Both writing to and reading from these bits
have no effect.
Some devices of the MB91520 series have ports missing. For details of which port is missing, see "1.16
Port function (General-Purpose I/O) Pins" in "CHAPTER:OVERVIEW". As for those bits allocated in the
missing ports, both writing and reading have no effect.
MB91520 Series
MN705-00010-1v0-E
408