Fujitsu FR81S User Manual
CHAPTER 11: I/O PORTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : I/O PORTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
12
4.4. Input Data Direct Register 00 to 19 : PDDR00 to 19
(Port Data Direct Register 00 to 19)
The bit configuration of input data direct register 00 to 19 is shown below.
These registers can always show the voltage levels of individual external pins. These registers can always
be read without condition.
PDDR00 to PDDR19 : Address 0E40
H
, 0E41
H
,
(Access : Byte, Half-word,
Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
P[7:0]
Initial
value
X
X
X
X
X
X
X
X
Attribute R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
[bit7 to bit0] P (Port) : Read bits
These bits can be read the value of the external pin.
PDDR0.P[7:0] is for external pins P007 to P000
PDDR1.P[7:0] is for external pins P017 to P010
PDDR2.P[7:0] is for external pins P027 to P020
(A similar process continues)
The assignment is as shown above.
P[n]
Operation
0
Low level
1
High level
PDDR13.P7, PDDR14.P[7:5, 1:0], PDDR15.P[7:6] are reserved bits. Both writing to and reading from
these bits have no effect.
PDDR13.P[6:5] are reserved bits in the dual clock products. Both writing to and reading from these bits
have no effect.
Some devices of the MB91520 series have ports missing. For details of which port is missing, see "1.16
Port function (General-Purpose I/O) Pins" in "CHAPTER:OVERVIEW". As for those bits allocated in the
missing ports, both writing and reading have no effect.
MB91520 Series
MN705-00010-1v0-E
407