Fujitsu FR81S User Manual

CHAPTER 17: PPG

4. Registers

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER

: PPG

FUJITSU SEMICONDUCTOR CONFIDENTIAL

4.3. PPG Duty Setting Register : PDUT0 to PDUT47

The bit configuration of the PPG duty setting register is shown.

The PPG duty setting register (PDUT) specifies the duty of the PPG output waveform.



PPG duty setting register (PDUT): Address Base_addr + 04

(Access:

Half-word, Word)

bit15

bit14

bit13

bit12

bit11

bit10

bit9

bit8

D15

D14

D13

D12

D11

D10

Initial value

Attribute

R1,W

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Initial value

Attribute

R1,W

[bit15 to bit0] D15 to D0 : PPG duty setting bits

D15 to D0

Function

Duty of the PPG output waveform

Note: These bits are write-only.

The PPG duty setting register has a buffer.

Data transfer from the buffer to the counter occurs automatically when a borrow occurs on the counter.

Be sure to set a value that is smaller than the value set to the PPG cycle setting register (PCSR) to the PPG

duty setting register.

If an equal value is set on the PPG duty setting register and the PPG cycle setting register, the result is as

follows:

⋅

If the polarity is normal (OSEL=0), the output is always "H".

⋅

If the polarity is inverted (OSEL=1), the output is always "L".

(The OSEL bit is the PPG output polarity selection bit of the PPG control status register (PCN).)

Notes:

⋅

If the PPG output waveform selection bit (PCN.OWFS)="0" (Normal Wave Form) is selected, the

waveform is output at the duty of a set value of PPG duty setting register.

⋅

If the PPG output waveform selection bit (PCN.OWFS)=1 (Center Aligned Wave Form) is selected, the

waveform is output at twice the duty of a set value of PPG duty setting register.

⋅

Be sure to access this register by the word (16-bit) format. If the byte is accessed to this register, the

value is not written at an upper and lower bit position.

MB91520 Series

MN705-00010-1v0-E

562