Fujitsu FR81S User Manual
CHAPTER 17: PPG
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
22
4.4. PPG Timer Register : PTMR0 to PTMR47
The bit configuration of the PPG timer register is shown.
The PPG timer register (PTMR) allows the PPG timer countdown value to be read.
PPG timer register (PTMR): Address Base_addr + 06
H
(Access: Half-word,
Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
Initial value
1
1
1
1
1
1
1
1
Attribute
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value
1
1
1
1
1
1
1
1
Attribute
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
[bit15 to bit0] D15 to D0 : PPG timer value bits
D15 to D0
Function
Timer down count value
Note: These bits are read-only.
The count value of the 17-bit down counter can be read from these bits.
⋅
If the Normal Wave Form (OWFS="0") is selected, the lower 16 bits are read.
⋅
If the Center Aligned Wave Form (OWFS="1") is selected, the upper 16 bits are read.
MB91520 Series
MN705-00010-1v0-E
563