Fujitsu FR81S User Manual
CHAPTER 19: BASE TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
17
Select whether to run the 16/32-bit timer individually by each channel or use the two channels as 32-bit timer
through a cascade connection. Set this bit for both channel 0 and channel 1.
T32 (channel 0)
T32 (channel 1)
Description
0
0
16-bit timer independent operation
respectively
0
1
Setting is prohibited
1
0
32-bit timer
1
1
Setting is prohibited
Note:
Change this bit after changing the FMD[2:0] to 000.(Once you have changed the FMD[2:0] to 000, set the
T32 bit and FMD[2:0] to a required value at the same time.)
[bit6 to bit4] FMD[2:0] (Function MoDe) : Timer function selection bits
These bits are used to select a function of base timer. To change these bits, go to 000 (reset mode) first, and set
it to another mode.
FMD[2:0]
Description
000
Reset mode
(Writing FMD = 000 will reverse the state of the base timer after the reset.
Each register will be reset to the initial value.)
001
16-bit PWM timer
010
16-bit PPG timer
011
16/32-bit reload timer
100
16/32-bit PWC timer
101
110
111
Setting is prohibited
[bit3] OSEL (Output SELect) : Output polarity selection bit
When this bit is set, the signal level (H/L) output from TOUT will be inverted.
OSEL
Description
0
Normal output
1
Inverted output
[bit2] MDSE (MoDe Select) : Mode selection bit
[Reload timer-PWM]
MB91520 Series
MN705-00010-1v0-E
650