Fujitsu FR81S User Manual
CHAPTER 23: 32-BIT INPUT CAPTURE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT INPUT CAPTURE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
8
4.1. Input Capture Data Register : IPCP
This section shows the bit configuration for the input capture data register.
This register can be used to hold and read the count value or the pulse width measurement data value of the
free-run timer using a change in the input signal from the external source as a trigger.
x: Channel number 4, 6, 8
y: Channel number 5, 7, 9
IPCPx (Input capture x): Address Base_addr+00
H
(Access: Word)
IPCPy (Input capture y): Address Base_addr+04
H
(Access: Word)
bit31
bit0
CP[31:0]
Initial value X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
Attribute
R,WX
[bit31 to bit0] CP[31:0] :
When MSCL.MSCx or MSCy is "0", this register indicates the value of free-run timer at the edge detection.
When MSCL.MSCx or MSCy is "1", this register indicates the value of the pulse width at the edge detection.
Note:
When accessing this register, use a word access instruction. No data can be written to this register.
MB91520 Series
MN705-00010-1v0-E
883