Fujitsu FR81S User Manual
CHAPTER 23: 32-BIT INPUT CAPTURE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT INPUT CAPTURE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
9
4.2. Input Capture Control Register : ICS
This section shows the bit configuration the input capture control register.
This register is used to control the input capture.
x: Channel number 4, 6, 8
y: Channel number 5, 7, 9
ICSxy (Input capture xy): Address Base_addr+0B
H
(Access: Byte, Half-word,
Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICPy
ICPx
ICEy
ICEx
EGy1
EGy0
EGx1
EGx0
Initial value
0
0
0
0
0
0
0
0
Attribute R(RM1),W R(RM1),W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7, bit6] ICPn : Input capture interrupt request flag
ICPn
State
Read
Write
0
No interrupt request
Clear the flag
1
Interrupt request present (edge detected)
No effect on operation
⋅
This flag will be set to "1" when the signal change (edge) selected in the capture effective edge selection
bit (EG[n1:n0]) is detected in the input signal from the external pin.
⋅
To enable the CPU interrupt request, you need to enable interrupt request enable setting (ICEn="1").
* ICPn: n corresponds to the input capture channel numbers.
[bit5, bit4] ICEn : Input capture interrupt request enabled
ICEn
Operation
0
Interrupt disabled
1
Interrupt enabled
An input capture interrupt is generated when the input capture interrupt request flag is set to "1" while the
input capture interrupt request enable bit is set to "1".
* ICEn: n corresponds to the input capture channel numbers.
[bit3 to bit0] EGn1, EGn0 : Input capture n effective edge selection
EGn1
EGn0
Edge selection
0
0
Input capture stopped
0
1
Rising edge
1
0
Falling edge
1
1
Both edges (rising and falling edges)
⋅
These bits are used to select the capture effective edge(s) for the input capture signal from the external pin.
⋅
The input capture will be in stop if the effective edge selection bit is "00
B
".
* EGn1, EGn0: n corresponds to the input capture channel numbers.
MB91520 Series
MN705-00010-1v0-E
884