Fujitsu FR81S User Manual
CHAPTER 23: 32-BIT INPUT CAPTURE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT INPUT CAPTURE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
10
4.3. LIN SYNCH FIELD Switching Register : LSYNS
This section shows the bit configuration for the LIN SYNCH FIELD switching register.
When the capture operation is enabled (ICS.EG[n1:n0] is other than "00") and input is switched while the
signal level of the external pin input and the state of the LIN synch field detection signal (level) are different,
edges will be detected and will operate as capture effective edges.
LSYNS1 (Input capture 4-9): Address 0FDA
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
LSYN91 LSYN90 LSYN81 LSYN80 LSYN7
LSYN6
LSYN5
LSYN4
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
The input for the input capture must be switched while the capture is inactive (ICS.EG[n1:n0]=00).
[bit7, bit6] LSYN91, LSYN90 : Input capture ch.9 input selection
LSYN91, LSYN90
Input selection
00
External pin input (ICU9)
01
LIN synch field detection signal input from the multi-function serial
interface ch.10.
10
LIN synch field detection signal input from the multi-function serial
interface ch.11.
11
Setting prohibited.
(Operation is not guaranteed.)
[bit5, bit4] LSYN81, LSYN80 : Input capture ch.8 input selection
LSYN81, LSYN80
Input selection
00
External pin input (ICU8)
01
LIN synch field detection signal input from the multi-function serial
interface ch.8.
10
LIN synch field detection signal input from the multi-function serial
interface ch.9.
11
Setting prohibited.
(Operation is not guaranteed.)
[bit3 to bit0] LSYN7 to LSYN4 : Input capture ch.4 to ch.7 input selection
LSYNn (n=4 to 7)
Input selection
0
External pin input (ICUn)
1
LIN synch field detection signal input from the multi-function serial
interface ch.n.
MB91520 Series
MN705-00010-1v0-E
885