Fujitsu FR81S User Manual
CHAPTER 23: 32-BIT INPUT CAPTURE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT INPUT CAPTURE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
12
4.5. Cycle and Pulse Width Measurement Control Register
(Upper bit) : MSCH
This section shows the cycle and pulse width measurement control register (upper bit).
This register is used to control the input capture.
x: Channel number 4, 6, 8
y: Channel number 5, 7, 9
MSCH45 (Input capture 45): Address 0F8A
H
(Access: Byte, Half-word, Word)
MSCH67 (Input capture 67): Address 0F8E
H
(Access: Byte, Half-word, Word)
MSCH89 (Input capture 89): Address 0FFE
H
(Access: Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CYCy
CYCx
PLSy
PLSx
OVCy
OVCx
OVPy
OVPx
Initial value
0
0
0
0
0
0
0
0
Attribute R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
[bit15, bit14] CYCn : Cycle measurement flag
CYCn
Explanation
0
Cycle data from falling edge to falling edge.
1
Cycle data from rising edge to rising edge.
⋅
These bits show that the data stored in the cycle measurement data register (MSCYn) is either rising cycle
or falling cycle. Whenever an effective edge is detected and measured, these bits are updated.
* CYCn : The number of n corresponds to the channel number of the input capture.
[bit13, bit12] PLSn : Pulse width measurement flag
PLSn
Explanation
0
Cycle data from falling edge to falling edge.
1
Cycle data from rising edge to rising edge.
⋅
These bits show that the data stored in the input capture data register (IPCPn) is either H pulse width or L
pulse width. Whenever an effective edge is detected and measured, these bits are updated.
* PLSn : The number of n corresponds to the channel number of the input capture.
[bit11, bit10] OVCn : Cycle measurement over flag
OVCn
Explanation
0
Cycle data from falling edge to falling edge.
1
Cycle data from rising edge to rising edge.
⋅
These bits show that the data stored in the cycle measurement data register (MSCYn) have exceeded the
maximum value. Whenever an effective edge is detected and measured, these bits are updated.
* OVCn : The number of n corresponds to the channel number of the input capture.
MB91520 Series
MN705-00010-1v0-E
887