Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
23
Signal description
External bus output signals are synchronized to the rising edge of SYSCLK.
ASX
Indicates the start of access. This also functions as the address strobe.
An "L" pulse is output for a period of 1 or 2 cycles from when the access starts.
A00 to A21
Outputs the address information of the access destination.
This is output from when the access starts and continues until the access finishes.
CSnX (n=0 to 3)
Indicates that the access destination address is within the corresponding CS area. External bus devices are
required to process requests from the bus only when this signal is "L". After the configured count has
finished from when the access started, "L" begins to be output, and this continues until the access finishes.
RDX
Indicates the period of the read strobe. After the configured count ends from when CSnX (n=0 to 3) is
driven, this outputs "L" for read access. This returns to output "H" after the read auto wait count has ended.
The external bus device is required to return valid data in D16 to D31 within the period where RDX="L".
This module fetches the D16 to D31 data into the internal buffer on the rising edge of the final SYSCLK
within the period where RDX="L".
D16 to D31
The external bus device is required to return valid data in D16 to D31 within the period where RDX="L".
This module fetches the D16 to D31 data into the internal buffer on the rising edge of the final SYSCLK
within the period where RDX="L".
MB91520 Series
MN705-00010-1v0-E
1222