Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
67
Figure 5-4 Example of PLL/SSCG Mode Setting Main → PLL/SSCG
Yes
Main clock mode is confirmed.
Yes
PLL/SSCG clock stabilization wait time is set.
The SSCG use is judged.
No
Yes
Select SSCG
Select PLL
Multiplication rate of PLL is set.
Multiplication rate of PLL is set.
(For CAN and OCD)
Multiplication rate of SSCG is set.
The method of SSCG's spread is set.
The gear use is judged.
No
Yes
The gear is set to the valid status.
The gear is set to the invalid status.
Setting of gear step
No
Yes
PLL/SSCG clock oscillation stabilization wait timer
interrupt flag is clear.
PLL/SSCG clock oscillation stabilization
wait timer interrupt to effective
The operation of PLL/SSCG starts
The operation of PLL/SSCG begins.
PLL/SSCG clock oscillation
stabilization is fixed.
No
The PLL/SSCG clock operation stability is judged.
Yes
Dividing various clocks (CPU/Peripheral) is set.
When SSCG is used, peripheral resource is judged and whether it operates with PLL clock is judged.
When PLL is used, it is always synchronization
No
Yes
Dividing the asynchronous peripheral clock is set.
The relation of the CPU/peripheral clock
is set asynchronously.
The relation of the CPU/peripheral clock is set
synchronously.
When PLL/SSCG clock exceeds 80MHz, insert wait cycle into FLASH access.
Change to the PLL/SSCG clock
No
Confirm whether the source clock has switched PLL/SSCG.
Yes
When the gear is used, the gear is begun.
No
Yes
No
It is confirmed that the clock
has low-speed stopped.
Yes
Gear Start
No
The gear completion is confirmed.
Yes
Start
CMONR.CKM=00
CSELR.CKS=00
PLLCR.POSW
CCCGRCR0.GREN=1
Is the gear used?
CCCGRCR1.GRSTP
CCCGRCR1.GRSTN
CCCGRCR2.GRLP
CSELR.PCEN=1
CMONR.PCRDY=1
DIVR0.DIVB
DIVR2.DIVP
DIVR2.DIVP
SACR.M=1
CSELR.CKS=10
CMONR.CKM=10
CCCGRCR0.GREN=0
Is the gear used?
CCCGRCR0.GRSTS=00
CCCGRCR0.GRSTR=1
CCCGRCR0.GRSTS=10
PLL/SSCG operation
Is the SSCG used?
CCPSSELR.PCSEL=1
CCPSSELR.PCSEL=0
CCPSDIVR.SODS
CCSSFBR0.NDIV
CCSSFBR1.PDIV
PLLCR.PDS
CCPSDIVR.PODS
CCPLLFBR.IDIV
PLLCR.PDS
CCPSDIVR.PODS
CCPLLFBR.IDIV
CCSSCCR0.SFREQ
CCSSCCR0.SMODE
CCSSCCR0.SSEN
CCSSCCR1.RATESEL
Peripheral resource
Asynchronously ?
SACR.M=0
PICD.PDIV
FCTLR.FAW
Is the interrupt used?
PTMCR.PTIF=0
PTMCR.PTIE=0
CSELR.PCEN=1
PLL Oscillation stabilization
wait timer interrupt generation
No
Yes
Yes
Yes
Yes
Yes
Yes
MB91520 Series
MN705-00010-1v0-E
228