Intel 2760QM FF8062701065300 User Manual
Product codes
FF8062701065300
Electrical Specifications
64
Datasheet, Volume 1
7.5.3
Signal DC Specifications
DC specifications are defined at the processor pads, unless otherwise noted. DC
specifications are only valid while meeting specifications for case temperature (T
specifications are only valid while meeting specifications for case temperature (T
CASE
specified in the processor Thermal Mechanical Specification and Design Guide; see
Section 1.7, “Related Documents”
), clock frequency, and input voltages. Care should be
taken to read all notes associated with each specification.
Notes:
1.
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
The voltage rail V
CCD
will be set to 1.50 V nominal.
3.
V
IL
is the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
4.
V
IH
is the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
5.
V
IH
and V
OH
may experience excursions above V
CCD
.
Table 7-12. DDR3 Signal DC Specifications
Symbol
Parameter
Min
Typ
Max
Units
Notes
1
I
IL
Input Leakage Current
-500
—
+500
uA
10
Data Signals
V
IL
Input Low Voltage
—
—
0.43*V
CCD
V
2, 3
V
IH
Input High Voltage
0.57*V
CCD
—
V
2, 4, 5
R
ON
DDR3 Data Buffer On
Resistance
Resistance
21
—
31
6
Data ODT
On-Die Termination for Data
Signals
Signals
45
90
90
—
55
110
8
Reference Clock Signals, Command, and Data Signals
V
OL
Output Low Voltage
—
(V
CCD
/ 2)* (R
ON
/(R
ON
+R
VTT_TERM
))
—
V
2, 7
V
OH
Output High Voltage
—
V
CCD
– ((V
CCD
/ 2)*
(R
ON
/(R
ON
+R
VTT_TERM
))
—
V
2, 5, 7
Reference Clock Signal
R
ON
DDR3 Clock Buffer On
Resistance
Resistance
21
—
31
6
Command Signals
R
ON
DDR3 Command Buffer On
Resistance
Resistance
16
—
24
6
R
ON
DDR3 Reset Buffer On
Resistance
Resistance
25
—
75
6
V
OL_CMOS1.5v
Output Low Voltage, Signals
DDR_RESET_ C{01/23}_N
DDR_RESET_ C{01/23}_N
—
—
0.2*V
CCD
V
1, 2
V
OH_CMOS1.5v
Output High Voltage, Signals
DDR_RESET_ C{01/23}_N
DDR_RESET_ C{01/23}_N
0.9*V
CCD
—
—
V
1, 2
IIL_CMOS1.5v
Input Leakage Current
-100
—
+100
uA
1, 2
Control Signals
R
ON
DDR3 Control Buffer On
Resistance
Resistance
21
—
31
6
DDR01_RCOMP[0]
COMP Resistance
128.7
130
131.3
9, 12
DDR01_RCOMP[1]
COMP Resistance
25.839
26.1
26.361
9, 12
DDR01_RCOMP[2]
COMP Resistance
198
200
202
9, 12
DDR23_RCOMP[0]
COMP Resistance
128.7
130
131.3
9, 12
DDR23_RCOMP[1]
COMP Resistance
25.839
26.1
26.361
9, 12
DDR23_RCOMP[2]
COMP Resistance
198
200
202
9, 12
Miscellaneous Signals
V
IL
Input Low Voltage
DRAM_PWR_OK_C{01/23}
DRAM_PWR_OK_C{01/23}
—
—
0.55*VCCD
– 0.2
V
2, 3, 11,
13
V
IH
Input High Voltage
DRAM_PWR_OK_C{01/23}
DRAM_PWR_OK_C{01/23}
0.55*VCCD
+0.2
—
—
V
2, 4, 5,
11, 13