Intel 2760QM FF8062701065300 User Manual
Product codes
FF8062701065300
Datasheet, Volume 1
65
Electrical Specifications
6.
This is the pull-down driver resistance. Reset drive does not have a termination.
7.
R
VTT_TERM
is the termination on the DIMM and not controlled by the processor. Refer to the applicable DIMM
datasheet.
8.
The minimum and maximum values for these signals are programmable by BIOS to one of the pairs.
9.
COMP resistance must be provided on the system board with 1% resistors.
10. Input leakage current is specified for all DDR3 signals.
11. DRAM_PWR_OK_C{01/23} must have a maximum of 30 ns rise or fall time over VCCD * 0.55 + 300 mV
11. DRAM_PWR_OK_C{01/23} must have a maximum of 30 ns rise or fall time over VCCD * 0.55 + 300 mV
and -200 mV and the edge must be monotonic.
12. The DDR01/23_RCOMP error tolerance is ±5% from the compensated value.
13. DRAM_PWR_OK_C{01/23}: Data Scrambling should be enabled for production environments. Disabling
13. DRAM_PWR_OK_C{01/23}: Data Scrambling should be enabled for production environments. Disabling
Data scrambling can be used for debug and testing purposes only. Running systems with Data Scrambling
off will make the configuration out of specification. For details, refer to Volume 2 of the Datasheet.
off will make the configuration out of specification. For details, refer to Volume 2 of the Datasheet.
Notes:
1.
1.
V
TTD
supplies the PECI interface. PECI behavior does not affect V
TTD
min/max specification
2.
It is expected that the PECI driver will take into account, the variance in the receiver input thresholds and
consequently, be able to drive its output within safe limits (-0.150 V to 0.275*V
consequently, be able to drive its output within safe limits (-0.150 V to 0.275*V
TTD
for the low level and
0.725*V
TTD
to V
TTD
+0.150 V for the high level).
3.
The leakage specification applies to powered devices on the PECI bus.
4.
One node is counted for each client and one node for the system host. Extended trace lengths might appear
as additional nodes.
as additional nodes.
5.
Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently
limit the maximum bit rate at which the interface can operate.
limit the maximum bit rate at which the interface can operate.
Table 7-13. PECI DC Specifications
Symbol
Definition and Conditions
Min
Max
Units
Figure
Notes
1
V
In
Input Voltage Range
-0.150
V
TTD
V
V
Hysteresis
Hysteresis
0.100 * V
TTD
—
V
V
N
Negative-edge threshold voltage
0.275 * V
TTD
0.500 * V
TTD
V
7-1
2
V
P
Positive-edge threshold voltage
0.550 * V
TTD
0.725 * V
TTD
V
7-1
2
I
SOURCE
High level output source
V
V
OH
= 0.75 * V
TT
-6.0
—
mA
I
Leak+
High impedance state leakage to
V
V
TTD
(V
leak
= V
OL
)
N/A
50
µA
3
I
Leak-
High impedance leakage to GND
(V
(V
leak
= V
OH
)
N/A
25
µA
3
C
Bus
Bus capacitance per node
N/A
10
pF
4,5
V
Noise
Signal noise immunity above
300 MHz
300 MHz
0.100 * V
TTD
N/A
V
p-p