Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
The Processor Architecture Overview
28
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
• PCI Express Interfaces: The I/O module incorporates PCI Express interface. The 
processor can support up to 32 lanes of PCI Express. Following are key attributes of 
the PCI Express interface:
— Gen3 speeds at 8 GT/s (no 8b/10b encoding)
— 2 X16 interfaces, each can be bifurcated down to two x8 or four x4 (or 
combinations)
• DMI2 Interface to the PCH: The platform requires an interface to the legacy 
Southbridge (PCH) which provides basic, legacy functions required for the 
server/workstation platforms and operating systems. Since only one PCH is 
required for the system, any sockets which do not connect to PCH could use this 
port as a standard x4 PCI Express 2.0 interface.
• Integrated IOAPIC: Provides support for PCI Express devices implementing 
legacy interrupt messages without interrupt sharing
• Intel
®
 QuickData Technology: Used for efficient, high bandwidth data 
movement between two locations in memory or from memory to I/O
2.2.9
Config Agent (Ubox)
The UBox acts as the centralized unit for a variety of non-coherent type of transactions 
and functions:
• The target for interrupts. The UBox dispatches interrupts to the appropriate core.
• Decodes and routes transactions to uncore registers.
• Implements time stamp counters, scratch pad registers, PerfMon infrastructure 
support, and so forth.
• Serializes locks/unlock, Quiescent messages to the Lock Master in the legacy 
socket. 
Note:
The Lock Master must be legacy socket with socket ID[3,1:0]=[0,0,0].
2.2.10
Performance Monitor (PerfMon)
The processor implements an exhaustive set of counters designed to count and monitor 
events used for tracking performance. By combining the counts from different events, 
system software can determine the performance characteristics of the processor 
platform.
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