Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
29
Datasheet Volume Two: Functional Description, February 2014
Cbo Functional Description
3
Cbo Functional Description
The Intel Xeon processor E7 v2 product family core to the last level cache (LLC) 
interface is managed by the LLC coherence unit (Cbo). The Cbo handles all core and 
PCIe to Intel QuickPath Interconnect messages and system interface logic. There is at 
most one Cbo per core in a given socket. The LLC is 20-ways associative, and is an 
inclusive cache for the mid level cache in the cores.
Cbo cache coherence engine maintains cache coherency that handles access to the last 
level cache and generates transactions back to the core or system interconnect. The 
Cbo also ensures transaction conflicts are properly handled. The Cbo contains the TOR 
(Table Of Requests) that holds all pending transactions.
3.1
Basic Flows 
The Cbo supports three types of transactions:
1. Core/IIO initiated requests
2. Intel QPI external snoops
3. LLC capacity eviction
Each transaction has an associated entry in the Table of Requests (the TOR). The TOR 
entry holds information required by the Cbo to uniquely identify the request, in addition 
to the address and transaction type, and state elements required to track the current 
status of the transaction.
3.1.1
Handling Core/IIO Request
In general, there are two kinds of core/IIO requests:
Coherent request: Coherent requests are requests to access a memory address that 
is mapped to the coherent address space. They are usually used to transfer data at a 
cache line granularity and/or to change the state of a cache line. The most common 
coherent requests are Data and Code Reads, RFOs (Read for ownership), ItoMs 
(acquire ownership w/o reading the line) and Writebacks (write a Modified data from 
MLC to LLC).
The Coherent requests are serviced by the Cbo that holds the LLC slice for the specified 
address, determined by the hashing function.
Non Coherent request: Non-coherent requests are either data accesses that map to 
non-coherent address space (like Memory Mapped IO), or they are non-memory 
requests like IO read/write, interrupts/events, and so forth.
When non-coherent requests accesses to non-coherent memory, they are sent to the 
Cbo according to the hash of the address just like coherent requests. The non-coherent 
requests which do not target memory are always sent to the Cbo that is attached to the 
core which generates the request (also referred to as the collocated slice).
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