Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
2009-2011 Microchip Technology Inc.
DS39960D-page 363
PIC18F87K22 FAMILY
23.4
Selecting and Configuring
Automatic Acquisition Time
Automatic Acquisition Time
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit.
This occurs when the ACQT<2:0> bits
(ADCON2<5:3>) remain in their Reset state (‘000’),
which is compatible with devices that do not offer
programmable acquisition times.
If desired, the ACQTx bits can be set to select a pro-
grammable acquisition time for the A/D module. When
the GO/DONE bit is set, the A/D module continues to
sample the input for the selected acquisition time, then
automatically begins a conversion. Since the acquisi-
tion time is programmed, there may be no need to wait
for an acquisition time between selecting a channel and
setting the GO/DONE bit.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
acquisition time that occurs each time the GO/DONE
bit is set.
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit.
This occurs when the ACQT<2:0> bits
(ADCON2<5:3>) remain in their Reset state (‘000’),
which is compatible with devices that do not offer
programmable acquisition times.
If desired, the ACQTx bits can be set to select a pro-
grammable acquisition time for the A/D module. When
the GO/DONE bit is set, the A/D module continues to
sample the input for the selected acquisition time, then
automatically begins a conversion. Since the acquisi-
tion time is programmed, there may be no need to wait
for an acquisition time between selecting a channel and
setting the GO/DONE bit.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
23.5
Selecting the A/D Conversion
Clock
Clock
The A/D conversion time per bit is defined as T
AD
. The
A/D conversion requires 14 T
AD
per 12-bit conversion.
The source of the A/D conversion clock is
software-selectable.
The possible options for T
software-selectable.
The possible options for T
AD
are:
• 2 T
OSC
• 4 T
OSC
• 8 T
OSC
• 16 T
OSC
• 32 T
OSC
• 64 T
OSC
• Using the internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(T
For correct A/D conversions, the A/D conversion clock
(T
AD
) must be as short as possible, but greater than
the minimum T
AD
. (For more information, see
Parameter
.)
shows the resultant T
AD
times derived from
the device operating frequencies and the A/D clock
source selected.
source selected.
TABLE 23-1:
T
AD
vs. DEVICE OPERATING
FREQUENCIES
23.6
Configuring Analog Port Pins
The ANCON0, ANCON1, ANCON2, TRISA, TRISF,
TRISG and TRISH registers control the operation of the
A/D port pins. The port pins needed as analog inputs
must have their corresponding TRISx bits set (input). If
the TRISx bit is cleared (output), the digital output level
(V
TRISG and TRISH registers control the operation of the
A/D port pins. The port pins needed as analog inputs
must have their corresponding TRISx bits set (input). If
the TRISx bit is cleared (output), the digital output level
(V
OH
or V
OL
) will be converted.
The A/D operation is independent of the state of the
CHS<3:0> bits and the TRISx bits.
CHS<3:0> bits and the TRISx bits.
AD Clock Source (T
AD
)
Maximum
Device
Frequency
Operation
ADCS<2:0>
2 T
OSC
000
2.50 MHz
4 T
OSC
100
5.00 MHz
8 T
OSC
001
10.00 MHz
16 T
OSC
101
20.00 MHz
32 T
OSC
010
40.00 MHz
64 T
OSC
110
64.00 MHz
RC
)
x11
1.00 MHz
Note 1:
The RC source has a typical T
AD
time of
4
s.
2:
For device frequencies above 1 MHz, the
device must be in Sleep mode for the
entire conversion or the A/D accuracy may
be out of specification.
device must be in Sleep mode for the
entire conversion or the A/D accuracy may
be out of specification.
Note 1:
When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
2:
Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.