Microchip Technology MA330028 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 136
2011-2013 Microchip Technology Inc.
REGISTER 7-4:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
GIE
DISI
SWTRAP
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
GIE:
Global Interrupt Enable bit
1
= Interrupts and associated IE bits are enabled
0
= Interrupts are disabled, but traps are still enabled
bit 14
DISI:
DISI Instruction Status bit
1
= DISI instruction is active
0
= DISI instruction is not active
bit 13
SWTRAP:
Software Trap Status bit
1
= Software trap is enabled
0
= Software trap is disabled
bit 12-3
Unimplemented:
Read as ‘0’
bit 2
INT2EP:
External Interrupt 2 Edge Detect Polarity Select bit
1
= Interrupt on negative edge
0
= Interrupt on positive edge
bit 1
INT1EP:
External Interrupt 1 Edge Detect Polarity Select bit
1
= Interrupt on negative edge
0
= Interrupt on positive edge
bit 0
INT0EP:
External Interrupt 0 Edge Detect Polarity Select bit
1
= Interrupt on negative edge
0
= Interrupt on positive edge