Microchip Technology MA330028 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 138
2011-2013 Microchip Technology Inc.
REGISTER 7-7:
INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
—
—
—
—
ILR3
ILR2
ILR1
ILR0
bit 15
bit 8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
VECNUM7
VECNUM6
VECNUM5
VECNUM4
VECNUM3
VECNUM2
VECNUM1
VECNUM0
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented:
Read as ‘0’
bit 11-8
ILR<3:0>:
New CPU Interrupt Priority Level bits
1111
= CPU Interrupt Priority Level is 15
•
•
•
0001
•
•
0001
= CPU Interrupt Priority Level is 1
0000
= CPU Interrupt Priority Level is 0
bit 7-0
VECNUM<7:0>:
Vector Number of Pending Interrupt bits
11111111
= 255, Reserved; do not use
•
•
•
•
•
00001001
= 9, IC1 – Input Capture 1
00001000
= 8, INT0 – External Interrupt 0
00000111
= 7, Reserved; do not use
00000110
= 6, Generic soft error trap
00000101
= 5, DMAC error trap
00000100
= 4, Math error trap
00000011
= 3, Stack error trap
00000010
= 2, Generic hard trap
00000001
= 1, Address error trap
00000000
= 0, Oscillator fail trap