Microchip Technology MA330028 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 156
2011-2013 Microchip Technology Inc.
9.3
Oscillator Control Registers
REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER
)
U-0
R-0
R-0
R-0
U-0
R/W-y
R/W-y
R/W-y
—
COSC2
COSC1
COSC0
—
NOSC2
NOSC1
NOSC0
bit 15
bit 8
R/W-0
R/W-0
R-0
U-0
R/W-0
U-0
U-0
R/W-0
CLKLOCK
IOLOCK
LOCK
—
CF
(
)
—
—
OSWEN
bit 7
bit 0
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented:
Read as ‘0’
bit 14-12
COSC<2:0>:
Current Oscillator Selection bits (read-only)
111
= Fast RC Oscillator (FRC) with Divide-by-n
110
= Fast RC Oscillator (FRC) with Divide-by-16
101
= Low-Power RC Oscillator (LPRC)
100
= Reserved
011
= Primary Oscillator (XT, HS, EC) with PLL
010
= Primary Oscillator (XT, HS, EC)
001
= Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL)
000
= Fast RC Oscillator (FRC)
bit 11
Unimplemented:
Read as ‘0’
bit 10-8
NOSC<2:0>:
New Oscillator Selection bits
(
)
111
= Fast RC Oscillator (FRC) with Divide-by-n
110
= Fast RC Oscillator (FRC) with Divide-by-16
101
= Low-Power RC Oscillator (LPRC)
100
= Reserved
011
= Primary Oscillator (XT, HS, EC) with PLL
010
= Primary Oscillator (XT, HS, EC)
001
= Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL)
000
= Fast RC Oscillator (FRC)
bit 7
CLKLOCK:
Clock Lock Enable bit
1
= If (FCKSM0 = 1), then clock and PLL configurations are locked; if (FCKSM0 = 0), then clock and
PLL configurations may be modified
0
= Clock and PLL selections are not locked, configurations may be modified
bit 6
IOLOCK:
I/O Lock Enable bit
1
= I/O lock is active
0
= I/O lock is not active
bit 5
LOCK:
PLL Lock Status bit (read-only)
1
= Indicates that PLL is in lock or PLL start-up timer is satisfied
0
= Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
Note 1:
Writes to this register require an unlock sequence. Refer to “Oscillator” (DS70580) in the “dsPIC33/
PIC24 Family Reference Manual”
PIC24 Family Reference Manual”
(available from the Microchip web site) for details.
2:
Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transitional clock source between the two PLL modes.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transitional clock source between the two PLL modes.
3:
This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an
actual oscillator failure and trigger an oscillator failure trap.
actual oscillator failure and trigger an oscillator failure trap.