Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual

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Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

This register controls the closed loop thermal response of the DRAM thermal throttle 
logic. It supports immediate thermal throttle and 2X refresh. In addition, the register is 
used to configure the throttling duty cycle.

Compared against bits [36:29] of virtual temperature of each rank stored in 
RANK_VIRTUAL_TEMP to determine the throttle point. Recommended value for each 
rank is 255.

When there are more than 4 ranks attached to the channel, the thermal throttle logic is 
shared. 

31:18

RO

0

17:8

RW

64

MIN_THROTTLE_DUTY_CYC
This parameter represents the minimum number of DCLKs of operation 

allowed after throttling. In order to provide actual command opportunities, 

the number of clocks between CKE deassertion and first command should 

be considered.

7:5

RO

0

4

RW

0

REF_2X_NOW
Direct control of dynamic 2X refresh if direct throttling is enabled.

3:0

RW

0

THROTTLE_NOW
Throttler Vector to directly control throttling if 

MC_THERMAL_CONTROL.THROTTLE_MODE == 2.

31:24

RW

0

RANK3. Rank 3 throttle offset.

23:16

RW

0

RANK2. Rank 2 throttle offset.

15:8

RW

0

RANK1. Rank 1 throttle offset.

7:0

RW

0

RANK0. Rank 0 throttle offset.