Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
269
Processor Uncore Configuration Registers
4.13.9
MC_RANK_VIRTUAL_TEMP0
MC_RANK_VIRTUAL_TEMP1
This register contains the 8 most significant bits [37:30] of the virtual temperature of
each rank. The difference between the virtual temperature and the sensor temperature
can be used to determine how fast fan speed should be increased. The value stored is
right shifted one bit to the right with respect to the corresponding MC_Throttle_Offset
register value. For example when When a rank throttle offset is set to 40h, the value
read from the corresponding in MC_RANK_VIRTUAL_TEMP register is 20h.
each rank. The difference between the virtual temperature and the sensor temperature
can be used to determine how fast fan speed should be increased. The value stored is
right shifted one bit to the right with respect to the corresponding MC_Throttle_Offset
register value. For example when When a rank throttle offset is set to 40h, the value
read from the corresponding in MC_RANK_VIRTUAL_TEMP register is 20h.
When there are more than 4 ranks attached to the channel, the thermal throttle logic is
shared.
shared.
4.13.10 MC_DDR_THERM_COMMAND0
MC_DDR_THERM_COMMAND1
This register contains the command portion of the functionality of the
PM_EXT_TS#[1:0] signals.
PM_EXT_TS#[1:0] signals.
Device:
4, 5
Function: 3
Offset:
98h
Access as a DWord
Bit
Attr
Default
Description
31:24
RO
0
RANK3. Rank 3 virtual temperature.
23:16
RO
0
RANK2. Rank 2 virtual temperature.
15:8
RO
0
RANK1. Rank 1 virtual temperature.
7:0
RO
0
RANK0. Rank 0 virtual temperature.
Device:
4, 5
Function: 3
Offset:
9Ch
Access as a DWord
Bit
Attr
Default
Description
31:4
RO
0
Reserved
3
RW
0
THROTTLE
Force throttling when DDR_THERM# pin is asserted.
Force throttling when DDR_THERM# pin is asserted.
2
RW
0
REF_2X
Force 2x refresh as long as DDR_THERM# is asserted.
Force 2x refresh as long as DDR_THERM# is asserted.
1
RW
0
DISABLE_EXTTS
DDR_THERM# pin disable, forces signal to look deasserted, thus a 1.
DDR_THERM# pin disable, forces signal to look deasserted, thus a 1.
0
RW
0
LOCK
When set, all bits in this register are RO and cannot be written.
When set, all bits in this register are RO and cannot be written.