Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
271
System Address Map
5
System Address Map
5.1
Introduction
This chapter provides a basic overview of the system address map and describes how
the processor IIO comprehends and decodes the various regions in the system address
map. The term “IIO” in this chapter refers to processor IIO (in both End Point and Dual
IIO Proxy modes). This chapter does not provide the full details of the platform system
address space as viewed by software and also it does not provide the details of
processor address decoding.
the processor IIO comprehends and decodes the various regions in the system address
map. The term “IIO” in this chapter refers to processor IIO (in both End Point and Dual
IIO Proxy modes). This chapter does not provide the full details of the platform system
address space as viewed by software and also it does not provide the details of
processor address decoding.
The IIO supports 64 GB (36 bit) of host address space and 64 KB+3 of addressable
I/O space. There is a programmable memory address space under the 1-MB region
which is divided into regions which can be individually controlled with programmable
attributes such as Disable, Read/Write, Write Only, or Read Only. Attribute
programming is described in
I/O space. There is a programmable memory address space under the 1-MB region
which is divided into regions which can be individually controlled with programmable
attributes such as Disable, Read/Write, Write Only, or Read Only. Attribute
programming is described in
. This section focuses on how the memory
space is partitioned and what the separate memory regions are used for. I/O address
space has simpler mapping, and is explained near the end of this section.
space has simpler mapping, and is explained near the end of this section.
The processor IIO supports 36 bits (35:0) of memory addressing on its Intel QuickPath
Interconnect interface. IIO also supports receiving and decoding 64 bits of address
from PCI Express. Memory transactions received from PCI Express that go above the
top of physical address space supported on Intel QuickPath Interconnect (which is
dependent on the Intel QuickPath Interconnect profile but is always less than or equal
to 2^40 for IIO) are reported as errors by IIO. The IIO as a requester would never
generate requests on PCI Express with any of Address Bits 63 to 40 set. For packets
that IIO receives from Intel QuickPath Interconnect and for packets that IIO receives
from PCIe, the IIO always performs a full 64-bit target address decoding. This means
that for the processor, Bits 36 to 63 of the address must be set to all zeros in order for
the IIO’s target address decoder to positively decode and acknowledge the packet.
Interconnect interface. IIO also supports receiving and decoding 64 bits of address
from PCI Express. Memory transactions received from PCI Express that go above the
top of physical address space supported on Intel QuickPath Interconnect (which is
dependent on the Intel QuickPath Interconnect profile but is always less than or equal
to 2^40 for IIO) are reported as errors by IIO. The IIO as a requester would never
generate requests on PCI Express with any of Address Bits 63 to 40 set. For packets
that IIO receives from Intel QuickPath Interconnect and for packets that IIO receives
from PCIe, the IIO always performs a full 64-bit target address decoding. This means
that for the processor, Bits 36 to 63 of the address must be set to all zeros in order for
the IIO’s target address decoder to positively decode and acknowledge the packet.
The IIO supports 16 bits of I/O addressing on its Intel QuickPath Interconnect
interface. IIO also supports receiving and decoding the full 32 bits of I/O address from
PCI Express. I/O transactions initiated by the processor on Intel QuickPath
Interconnect can have non-zero value for address bits 16 and above. This is an artifact
of the uncore logic in the processor. IIO’s outbound I/O address decoder must ignore
them when decoding the I/O address space. I/O requests received from PCI Express
that are beyond 64 KB are reported as errors by IIO. IIO as a requester would never
generate I/O requests on PCI Express with any of address bits 31 to 16 set.
interface. IIO also supports receiving and decoding the full 32 bits of I/O address from
PCI Express. I/O transactions initiated by the processor on Intel QuickPath
Interconnect can have non-zero value for address bits 16 and above. This is an artifact
of the uncore logic in the processor. IIO’s outbound I/O address decoder must ignore
them when decoding the I/O address space. I/O requests received from PCI Express
that are beyond 64 KB are reported as errors by IIO. IIO as a requester would never
generate I/O requests on PCI Express with any of address bits 31 to 16 set.
The IIO supports PCI configuration addressing up to 256 buses, 32 devices per bus and
8 functions per device. A single grouping of 256 buses, 32 devices per bus and
8 functions per device is referred to as a PCI segment. All configuration addressing
within an IIO and hierarchies below an IIO must be within one segment. IIO does not
support being in multiple PCI segments.
8 functions per device. A single grouping of 256 buses, 32 devices per bus and
8 functions per device is referred to as a PCI segment. All configuration addressing
within an IIO and hierarchies below an IIO must be within one segment. IIO does not
support being in multiple PCI segments.
for address map details when Intel VT-d is enabled.
Note:
In debug mode, some address bits in the Intel QuickPath Interconnect header are used
for passing source information and hence are not decoded for forwarding transactions.
For the processor, the IIO is always the legacy IIO and DMI is always the subtractive
decode port.
decode port.