Техническая Спецификация (EVAL-AD5560EBUZ)СодержаниеFeatures1Applications1General Description1Revision History3Functional Block Diagram4Specifications5Timing Characteristics13Timing Diagrams13Absolute Maximum Ratings15ESD Caution15Pin Configurations and Function Descriptions16Typical Performance Characteristics20Terminology28Theory of Operation29Force Amplifier29HW_INH Function29DAC Reference Voltage (VREF)29Open-Sense Detect (OSD) Alarm and Clamp29Device Under Test Ground (DUTGND)29DUTGND Kelvin Sense29Kelvin Alarm (KELALM)29GPO30Comparators30Current Clamps30Clamp Alarm Function (CLALM)30Clamp Enable Function (CLEN/LOAD)30Short-Circuit Protection30Guard Amplifier30Compensation Capacitors30Current Range Selection31High Current Ranges31Master and Slaves in Force Voltage (FV) Mode31Master in FV Mode, Slaves in Force Current (FI) Mode32Ideal Sequence for Gang Mode32Compensation for Gang Mode32System Force/Sense Switches32Die Temperature Sensor and Thermal Shutdown33Measure Output (MEASOUT)33VMID Voltage33Force Amplifier Stability36Safe Mode36Autocompensation Mode36Manual Compensation Mode36Poles and Zeros in a Typical System37Minimizing the Number of External Compensation Components37CFx Pins37CCx Pins37Extra Poles and Zeros in the AD556037The Effect of CCx37The Effect of CFx37The Effect of RZ37The Effect of RP37Compensation Strategies38Ensuring Stability into an Unknown Capacitor Up to a Maximum Value38Optimizing Performance for a Known Capacitor Using Autocompensation Mode38Adjusting the Autocompensation Mode39Dealing with Parallel Load Capacitors39DAC Levels39Force and Comparator DACs39Clamp DACs39OSD DAC40DUTGND DAC40Offset DAC40Offset and Gain Registers40Offset and Gain Registers for the Force Amplifier DAC40Offset and Gain Registers for the Comparator DACs40Offset and Gain Registers for the Clamp DACs40Reference Selection41Choosing AVDD/AVSS Power Supply Rails41Choosing HCAVSSx and HCAVDDx Supply Rails41Power Dissipation41Package Composition and Maximum Vertical Force42Slew Rate Control42Programmable Slew Rate42Ramp Function42Serial Interface44SPI Interface44SPI Write Mode44SDO Output44RESET Function44BUSY Function44LOAD Function44Register Update Rates45Control Registers46DPS and DAC Addressing46Readback Mode57DAC Readback57Power-On Default57Using the HCAVDDx and HCAVSSx Supplies59Power Supply Sequencing59Required External Components60Power Supply Decoupling61Applications Information62Thermal Considerations62Temperature Contour Map on the Top of the Package63TQFP_EP Package63BGA Package63Outline Dimensions64Ordering Guide65Размер: 1,7 МБСтраницы: 68Язык: EnglishПросмотреть