Инструкции для Philips S1D13505

Содержание

• S1D13505 TECHNICAL MANUAL

  1
  • Customer Support Information

    3
    • Comprehensive Support Tools

      3
    • Evaluation / Demonstration Board

      3
    • Chip Documentation

      3
    • Software

      3
    • Application Engineering Support

      3
• Product Brief

  5
  • DESCRIPTION

    5
  • FEATURES

    5
  • System Block Diagram

    6
• Hardware Functional Specification

  7
  • 1 Introduction

    17
    • 1.1 Scope

      17
    • 1.2 Overview Description

      17
  • 2 Features

    18
    • 2.1 Memory Interface

      18
    • 2.2 CPU Interface

      18
    • 2.3 Display Support

      19
    • 2.4 Display Modes

      19
    • 2.5 Display Features

      19
    • 2.6 Clock Source

      19
    • 2.7 Miscellaneous

      20
  • 3 Typical System Implementation Diagrams

    21
    • Figure 31: Typical System Diagram (SH-4 Bus)

      21
    • Figure 32: Typical System Diagram (SH-3 Bus)

      21
    • Figure 33: Typical System Diagram (MC68K Bus 1, 16-Bit 68000)

      22
    • Figure 34: Typical System Diagram (MC68K Bus 2, 32-Bit 68030)

      22
    • Figure 35: Typical System Diagram (Generic Bus)

      23
    • Figure 36: Typical System Diagram (NEC VR41xx (MIPS) Bus)

      23
    • Figure 37: Typical System Diagram (Philips PR31500/PR31700 Bus)

      24
    • Figure 38: Typical System Diagram (Toshiba TX3912 Bus)

      24
    • Figure 39: Typical System Diagram (Power PC Bus)

      25
    • Figure 310: Typical System Diagram (PC Card (PCMCIA) Bus)

      25
  • 4 Internal Description

    26
    • 4.1 Block Diagram Showing Datapaths

      26
    • 4.2 Block Descriptions

      26
      • 4.2.1 Register

        26
      • 4.2.2 Host Interface

        26
      • 4.2.3 CPU R/W

        26
      • 4.2.4 Memory Controller

        27
      • 4.2.5 Display FIFO

        27
      • 4.2.6 Cursor FIFO

        27
      • 4.2.7 Look-Up Tables

        27
      • 4.2.8 CRTC

        27
      • 4.2.9 LCD Interface

        27
      • 4.2.10 DAC

        27
      • 4.2.11 Power Save

        27
      • 4.2.12 Clocks

        27
  • 5 Pins

    28
    • 5.1 Pinout Diagram

      28
      • Figure 51: Pinout Diagram

        28
    • 5.2 Pin Description

      29
      • Key:

        29
      • 5.2.1 Host Interface

        29
        • Table 51: Host Interface Pin Descriptions 

          29
      • 5.2.2 Memory Interface

        35
        • Table 52: Memory Interface Pin Descriptions 

          35
      • 5.2.3 LCD Interface

        37
        • Table 52: LCD Interface Pin Descriptions 

          37
      • 5.2.4 CRT Interface

        37
        • Table 53: CRT Interface Pin Descriptions 

          37
      • 5.2.5 Miscellaneous

        38
        • Table 54: Miscellaneous Interface Pin Descriptions 

          38
    • 5.3 Summary of Configuration Options

      39
      • Table 55: Summary of Power On/Reset Options

        39
    • 5.4 Multiple Function Pin Mapping

      40
      • Table 56: CPU Interface Pin Mapping

        40
      • Table 57: Memory Interface Pin Mapping

        41
      • Table 58: LCD Interface Pin Mapping

        42
    • 5.5 CRT Interface

      43
      • Figure 53: External Circuitry for CRT Interface

        43
  • 6 D.C. Characteristics

    44
    • Table 61: Absolute Maximum Ratings

      44
    • Table 62: Recommended Operating Conditions

      44
    • Table 63: Electrical Characteristics for VDD = 5.0V typical 

      45
    • Table 64: Electrical Characteristics for VDD = 3.3V typical

      46
    • Table 65: Electrical Characteristics for VDD = 3.0V typical

      47
  • 7 A.C. Characteristics

    48
    • 7.1 CPU Interface Timing

      48
      • 7.1.1 SH-4 Interface Timing

        48
        • Figure 71: SH-4 Timing

          48
        • Table 71: SH-4 Timing

          49
      • 7.1.2 SH-3 Interface Timing

        50
        • Figure 72: SH-3 Timing

          50
        • Table 72: SH-3 Timing

          51
      • 7.1.3 MC68K Bus 1 Interface Timing (e.g. MC68000)

        52
        • Figure 73: MC68000 Timing

          52
        • Table 73: MC68000 Timing

          53
      • 7.1.4 MC68K Bus 2 Interface Timing (e.g. MC68030)

        54
        • Figure 74: MC68030 Timing

          54
        • Table 74: MC68030 Timing

          55
      • 7.1.5 PC Card Interface Timing

        56
        • Figure 75: PC Card Timing

          56
        • Table 75: PC Card Timing

          57
      • 7.1.6 Generic Interface Timing

        58
        • Figure 76: Generic Timing

          58
        • Table 76: Generic Timing

          59
      • 7.1.7 MIPS/ISA Interface Timing

        60
        • Figure 77: MIPS/ISA Timing

          60
        • Table 77: MIPS/ISA Timing

          61
      • 7.1.8 Philips Interface Timing (e.g. PR31500/PR31700)

        62
        • Figure 78: Philips Timing

          62
        • Table 78: Philips Timing

          63
        • Figure 79: Clock Input Requirement

          63
        • Table 79: Clock Input Requirements for BUSCLK using Philips local bus

          63
      • 7.1.9 Toshiba Interface Timing (e.g. TX3912)

        64
        • Figure 710: Toshiba Timing

          64
        • Table 710: Toshiba Timing

          65
        • Figure 711: Clock Input Requirement

          65
        • Table 711: Clock Input Requirements for BUSCLK using Toshiba local bus

          65
      • 7.1.10 Power PC Interface Timing (e.g. MPC8xx, MC68040, Coldfire)

        66
        • Figure 712: Power PC Timing

          66
        • Table 712: Power PC Timing

          67
    • 7.2 Clock Input Requirements

      68
      • Figure 713: Clock Input Requirement

        68
      • Table 713: Clock Input Requirements for CLKI divided down internally (MCLK = CLKI/2)

        68
      • Table 714: Clock Input Requirements for CLKI

        68
    • 7.3 Memory Interface Timing

      69
      • 7.3.1 EDO-DRAM Read/Write/Read-Write Timing

        69
        • Figure 714: EDO-DRAM Read/Write Timing

          69
        • Figure 715: EDO-DRAM Read-Write Timing

          70
        • Table 715: EDO-DRAM Read/Write/Read-Write Timing

          70
      • 7.3.2 EDO-DRAM CAS Before RAS Refresh Timing

        72
        • Figure 716: EDO-DRAM CAS Before RAS Refresh Timing

          72
        • Table 716: EDO-DRAM CAS Before RAS Refresh Timing

          72
      • 7.3.3 EDO-DRAM Self-Refresh Timing

        74
        • Figure 717: EDO-DRAM Self-Refresh Timing

          74
        • Table 717: EDO-DRAM Self-Refresh Timing

          74
      • 7.3.4 FPM-DRAM Read/Write/Read-Write Timing

        75
        • Figure 718: FPM-DRAM Read/Write Timing

          75
        • Figure 719: FPM-DRAM Read-Write Timing

          76
        • Table 718: FPM-DRAM Read/Write/Read-Write Timing

          76
      • 7.3.5 FPM-DRAM CAS Before RAS Refresh Timing

        78
        • Figure 720: FPM-DRAM CAS Before RAS Refresh Timing

          78
        • Table 719: FPM-DRAM CAS Before RAS Refresh Timing

          78
      • 7.3.6 FPM-DRAM Self-Refresh Timing

        79
        • Figure 721: FPM-DRAM Self-Refresh Timing

          79
        • Table 720: FPM-DRAM CBR Self-Refresh Timing

          79
    • 7.4 Power Sequencing

      80
      • 7.4.1 LCD Power Sequencing

        80
        • Figure 722: LCD Panel Power Off / Power On Timing. Drawn with LCDPWR set to active high polarity

          80
        • Table 721: LCD Panel Power Off/ Power On

          80
      • 7.4.2 Power Save Status

        81
        • Figure 723: Power Save Status and Local Bus Memory Access Relative to Power Save Mode

          81
        • Table 722: Power Save Status and Local Bus Memory Access Relative to Power Save Mode

          81
    • 7.5 Display Interface

      82
      • 7.5.1 4-Bit Single Monochrome Passive LCD Panel Timing

        82
        • Figure 724: 4-Bit Single Monochrome Passive LCD Panel Timing

          82
        • Figure 725: 4-Bit Single Monochrome Passive LCD Panel A.C. Timing

          83
        • Table 723: 4-Bit Single Monochrome Passive LCD Panel A.C. Timing

          83
      • 7.5.2 8-Bit Single Monochrome Passive LCD Panel Timing

        84
        • Figure 726: 8-Bit Single Monochrome Passive LCD Panel Timing

          84
        • Figure 727: 8-Bit Single Monochrome Passive LCD Panel A.C. Timing

          85
        • Table 724: 8-Bit Single Monochrome Passive LCD Panel A.C. Timing

          85
      • 7.5.3 4-Bit Single Color Passive LCD Panel Timing

        86
        • Figure 728: 4-Bit Single Color Passive LCD Panel Timing

          86
        • Figure 729: 4-Bit Single Color Passive LCD Panel A.C. Timing

          87
        • Table 725: 4-Bit Single Color Passive LCD Panel A.C. Timing

          87
      • 7.5.4 8-Bit Single Color Passive LCD Panel Timing (Format 1)

        88
        • Figure 730: 8-Bit Single Color Passive LCD Panel Timing (Format 1)

          88
        • Figure 731: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1)

          89
        • Table 726: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1)

          89
      • 7.5.5 8-Bit Single Color Passive LCD Panel Timing (Format 2)

        90
        • Figure 732: 8-Bit Single Color Passive LCD Panel Timing (Format 2)

          90
        • Figure 733: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2)

          91
        • Table 727: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2)

          91
      • 7.5.6 16-Bit Single Color Passive LCD Panel Timing

        92
        • Figure 734: 16-Bit Single Color Passive LCD Panel Timing

          92
        • Figure 735: 16-Bit Single Color Passive LCD Panel A.C. Timing

          93
        • Table 728: 16-Bit Single Color Passive LCD Panel A.C. Timing

          93
      • 7.5.7 8-Bit Dual Monochrome Passive LCD Panel Timing

        94
        • Figure 736: 8-Bit Dual Monochrome Passive LCD Panel Timing

          94
        • Figure 737: 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing

          95
        • Table 729: 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing

          95
      • 7.5.8 8-Bit Dual Color Passive LCD Panel Timing

        96
        • Figure 738: 8-Bit Dual Color Passive LCD Panel Timing

          96
        • Figure 739: 8-Bit Dual Color Passive LCD Panel A.C. Timing

          97
        • Table 730: 8-Bit Dual Color Passive LCD Panel A.C. Timing

          97
      • 7.5.9 16-Bit Dual Color Passive LCD Panel Timing

        98
        • Figure 740: 16-Bit Dual Color Passive LCD Panel Timing

          98
        • Figure 741: 16-Bit Dual Color Passive LCD Panel A.C. Timing

          99
        • Table 731: 16-Bit Dual Color Passive LCD Panel A.C. Timing

          99
      • 7.5.10 16-Bit TFT/D-TFD Panel Timing

        100
        • Figure 742: 16-Bit TFT/D-TFD Panel Timing

          100
        • Figure 743: TFT/D-TFD A.C. Timing

          101
        • Table 732: TFT/D-TFD A.C. Timing

          102
      • 7.5.11 CRT Timing

        103
        • Figure 744: CRT Timing

          103
        • Figure 745: CRT A.C. Timing

          104
  • 8 Registers

    105
    • 8.1 Register Mapping

      105
      • Table 81: S1D13505 Addressing

        105
    • 8.2 Register Descriptions

      105
      • 8.2.1 Revision Code Register

        105
      • 8.2.2 Memory Configuration Registers

        106
        • Table 82: DRAM Refresh Rate Selection

          106
      • 8.2.3 Panel/Monitor Configuration Registers

        107
        • Table 83: Panel Data Width Selection

          107
        • Table 84: FPLINE Polarity Selection

          109
        • Table 85: FPFRAME Polarity Selection

          111
      • 8.2.4 Display Configuration Registers

        112
        • Table 86: Simultaneous Display Option Selection

          112
        • Table 87: Bit-per-pixel Selection

          113
        • Table 88: Pixel Panning Selection

          115
      • 8.2.5 Clock Configuration Register

        116
        • Table 89: PCLK Divide Selection

          116
      • 8.2.6 Power Save Configuration Registers

        116
        • Table 810: Suspend Refresh Selection

          117
      • 8.2.7 Miscellaneous Registers

        117
        • Table 811: MA/GPIO Pin Functionality

          118
        • Table 812: Minimum Memory Timing Selection

          120
        • Table 813: RAS#-to-CAS# Delay Timing Select

          121
        • Table 814: RAS Precharge Timing Select

          122
        • Table 815: Optimal NRC, NRP, and NRCD values at maximum MCLK frequency

          122
        • Table 816: Minimum Memory Timing Selection

          123
      • 8.2.8 Look-Up Table Registers

        123
      • 8.2.9 Ink/Cursor Registers

        124
        • Table 817: Ink/Cursor Selection

          124
        • Table 818: Ink/Cursor Start Address Encoding

          126
        • Table 819: Recommended Alternate FRM Scheme

          127
  • 9 Display Buffer

    128
    • Table 91: S1D13505 Addressing

      128
    • Figure 91: Display Buffer Addressing

      128
    • 9.1 Image Buffer

      129
    • 9.2 Ink/Cursor Buffers

      129
    • 9.3 Half Frame Buffer

      129
  • 10 Display Configuration

    130
    • 10.1 Display Mode Data Format

      130
      • Figure 101: 1/2/4/8 Bit-per-pixel Format Memory Organization

        130
      • Figure 102: 15/16 Bit-per-pixel Format Memory Organization

        131
    • 10.2 Image Manipulation

      132
      • Figure 103: Image Manipulation

        132
  • 11 Look-Up Table Architecture

    133
    • 11.1 Monochrome Modes

      133
      • 1 Bit-per-pixel Monochrome mode

        133
        • Figure 111: 1 Bit-per-pixel Monochrome Mode Data Output Path

          133
      • 2 Bit-per-pixel Monochrome Mode

        133
        • Figure 112: 2 Bit-per-pixel Monochrome Mode Data Output Path

          133
      • 4 Bit-per-pixel Monochrome Mode

        134
        • Figure 113: 4 Bit-per-pixel Monochrome Mode Data Output Path

          134
    • 11.2 Color Modes

      135
      • 1 Bit-per-pixel Color Mode

        135
        • Figure 114: 1 Bit-per-pixel Color Mode Data Output Path

          135
      • 2 Bit-per-pixel Color Mode

        136
        • Figure 115: 2 Bit-per-pixel Color Mode Data Output Path

          136
      • 4 Bit-per-pixel Color Mode

        137
        • Figure 116: 4 Bit-per-pixel Color Mode Data Output Path

          137
      • 8 Bit-per-pixel Color Mode

        138
        • Figure 117: 8 Bit-per-pixel Color Mode Data Output Path

          138
      • 15/16 Bit-per-pixel Color Modes

        138
  • 12 Ink/Cursor Architecture

    139
    • 12.1 Ink/Cursor Buffers

      139
      • Table 121: Ink/Cursor Start Address Encoding

        139
    • 12.2 Ink/Cursor Data Format

      139
      • Figure 121: Ink/Cursor Data Format

        139
      • Table 122: Ink/Cursor Color Select

        140
    • 12.3 Ink/Cursor Image Manipulation

      140
      • 12.3.1 Ink Image

        140
      • 12.3.2 Cursor Image

        140
        • Figure 122: Cursor Positioning

          140
  • 13 SwivelView™

    141
    • 13.1 Concept

      141
      • Figure 131: Relationship Between The Screen Image and the Image Residing in the Display Buffer

        141
    • 13.2 Image Manipulation in SwivelView

      142
    • 13.3 Physical Memory Requirement

      143
      • Table 132 Minimum DRAM Size Required for SwivelView

        144
    • 13.4 Limitations

      144
  • 14 Clocking

    145
    • 14.1 Maximum MCLK: PCLK Ratios

      145
      • Table 141: Maximum PCLK Frequency with EDO-DRAM

        145
      • Table 142: Maximum PCLK Frequency with FPM-DRAM

        146
    • 14.2 Frame Rate Calculation

      147
      • Table 143: Example Frame Rates with Ink Disabled

        147
    • 14.3 Bandwidth Calculation

      149
      • Bandwidth during non display period

        149
      • Bandwidth during display period

        149
        • Table 144: Number of MCLKs required for various memory access

          149
        • Table 145: Total # MCLKs taken for Display refresh

          150
      • Average Bandwidth

        150
        • Table 146: Theoretical Maximum Bandwidth M byte/sec, Cursor/Ink disabled

          151
  • 15 Power Save Modes

    153
    • Table 151: Power Save Mode Function Summary

      153
    • Table 152: Pin States in Power-save Modes

      153
  • 16 Mechanical Data

    154
    • Figure 161: Mechanical Drawing QFP15

      154
• Programming Notes and Examples

  155
  • Table of Contents

    157
  • List of Tables

    161
  • List of Figures

    163
  • 1 Introduction

    165
  • 2 Initialization

    166
    • Table 21: S1D13505 Initialization Sequence

      166
    • 2.1 Miscellaneous

      169
  • 3 Memory Models

    170
    • 3.1 Display Buffer Location

      170
      • 3.1.1 Memory Organization for One Bit-Per-Pixel (2 Colors/Gray Shades)

        170
        • Figure 31: Pixel Storage for 1 Bpp (2 Colors/Gray Shades) in One Byte of Display Buffer

          170
      • 3.1.2 Memory Organization for Two Bit-Per-Pixel (4 Colors/Gray Shades)

        171
        • Figure 32: Pixel Storage for 2 Bpp (4 Colors/Gray Shades) in One Byte of Display Buffer

          171
      • 3.1.3 Memory Organization for Four Bit-Per-Pixel (16 Colors/Gray Shades)

        171
        • Figure 33: Pixel Storage for 4 Bpp (16 Colors/Gray Shades) in One Byte of Display Buffer

          171
      • 3.1.4 Memory Organization for Eight Bit-Per-Pixel (256 Colors/16 Gray Shades)

        172
        • Figure 34: Pixel Storage for 8 Bpp (256 Colors/16 Gray Shades) in One Byte of Display Buffer

          172
      • 3.1.5 Memory Organization for Fifteen Bit-Per-Pixel (32768 Colors/16 Gray Shades)

        172
        • Figure 35: Pixel Storage for 15 Bpp (32768 Colors/16 Gray Shades) in Two Bytes of Display Buffer

          172
      • 3.1.6 Memory Organization for Sixteen Bit-Per-Pixel (65536 Colors/16 Gray Shades)

        173
        • Figure 36: Pixel Storage for 16 Bpp (65536 Colors/16 Gray Shades) in Two Bytes of Display Buffer

          173
  • 4 Look-Up Table (LUT)

    174
    • 4.1 Look-Up Table Registers

      174
    • 4.2 Look-Up Table Organization

      175
      • Table 41: Look-Up Table Configurations

        175
      • Table 42: Recommended LUT Values for 1 Bpp Color Mode

        176
      • Table 43: Example LUT Values for 2 Bpp Color Mode

        176
      • Table 44: Suggested LUT Values to Simulate VGA Default 16 Color Palette

        177
      • Table 45: Suggested LUT Values to Simulate VGA Default 256 Color Palette

        178
      • Table 46: Recommended LUT Values for 1 Bpp Gray Shade

        180
      • Table 47: Suggested Values for 2 Bpp Gray Shade

        180
      • Table 48: Suggested LUT Values for 4 Bpp Gray Shade

        181
  • 5 Advanced Techniques

    183
    • 5.1 Virtual Display

      183
      • Figure 51: Viewport Inside a Virtual Display

        184
      • 5.1.1 Registers

        184
        • Figure 52: Memory Address Offset Registers

          184
      • 5.1.2 Examples

        185
    • 5.2 Panning and Scrolling

      185
      • 5.2.1 Registers

        186
        • Figure 53: Screen 1 Start Address Registers

          186
        • Table 51: Number of Pixels Panned Using Start Address

          187
        • Figure 54: Pixel Panning Register

          187
        • Table 52: Active Pixel Pan Bits

          187
      • 5.2.2 Examples

        187
    • 5.3 Split Screen

      189
      • Figure 55: 320x240 Single Panel For Split Screen

        189
      • 5.3.1 Registers

        189
        • Figure 56: Screen 1 Line Compare

          189
        • Figure 57: Screen 2 Display Start Address

          190
      • 5.3.2 Examples

        191
  • 6 LCD Power Sequencing and Power Save Modes

    192
    • 6.1 LCD Power Sequencing

      192
      • 6.1.1 Registers

        192
      • 6.1.2 LCD Power Disable

        193
    • 6.2 Software Power Save

      194
      • 6.2.1 Registers

        195
        • Table 61: Suspend Refresh Selection

          195
    • 6.3 Hardware Power Save

      196
  • 7 Hardware Cursor/Ink Layer

    197
    • 7.1 Introduction

      197
    • 7.2 Registers

      198
      • Table 71: Ink/Cursor Mode

        198
      • Table 72: Cursor/Ink Start Address Encoding

        200
    • 7.3 Limitations

      200
      • 7.3.1 Updating Hardware Cursor Addresses

        200
      • 7.3.2 Reg[29h] And Reg[2Bh]

        200
      • 7.3.3 Reg [30h]

        200
      • 7.3.4 No Top/Left Clipping on Hardware Cursor

        200
    • 7.4 Examples

      200
  • 8 SwivelView

    201
    • 8.1 Introduction To SwivelView

      201
    • 8.2 S1D13505 SwivelView

      201
    • 8.3 Registers

      201
    • 8.4 Limitations

      202
    • 8.5 Examples

      203
  • 9 CRT Considerations

    205
    • 9.1 Introduction

      205
      • 9.1.1 CRT Only

        205
      • 9.1.2 Simultaneous Display

        205
  • 10 Identifying the S1D13505

    206
  • 11 Hardware Abstraction Layer (HAL)

    207
    • 11.1 Introduction

      207
    • 11.2 Contents of the HAL_STRUCT

      207
    • 11.3 Using the HAL library

      208
    • 11.4 API for 13505HAL

      208
      • Table 111: HAL Functions

        208
    • 11.5 Initialization

      210
      • 11.5.1 General HAL Support

        212
      • 11.5.2 Advanced HAL Functions

        216
      • 11.5.3 Register / Memory Access

        218
      • 11.5.4 Color Manipulation

        221
      • 11.5.5 Drawing

        223
      • 11.5.6 Hardware Cursor

        225
      • 11.5.7 Ink Layer

        229
      • 11.5.8 Power Save

        232
    • 11.6 Porting LIBSE to a new target platform

      232
      • Figure 111: Components needed to build 13505 HAL application

        232
      • 11.6.1 Building the LIBSE library for SH3 target example

        233
      • 11.6.2 Building the HAL library for the target example

        234
      • 11.6.3 Building a complete application for the target example

        234
  • 12 Sample Code

    238
    • 12.1 Introduction

      238
      • 12.1.1 Sample code using the S1D13505 HAL API

        238
      • 12.1.2 Sample code without using the S1D13505 HAL API

        240
      • 12.1.3 Header Files

        249
        • Table 121: Passive Single Panel @ 320x240 with 40MHz Pixel Clock

          261
        • Table 122: Passive Single Panel @ 640x480 with 40MHz Pixel Clock

          261
        • Table 123: Passive Dual Panel @ 640x480 with 40MHz Pixel Clock

          262
        • Table 124: TFT Single Panel @ 640x480 with 25.175 MHz Pixel Clock

          262
• Register Summary

  263
  • REG[00h] Revision Code Register 1 (For S1D13505: Product Code=000011b, Revision Code=00b) RO

    263
  • REG[01h] Memory Configuration Register 1/0 RW

    263
  • REG[02h] Panel Type Register 1/0 RW

    263
  • REG[03h] Mod Rate Register RW

    263
  • REG[04h] Horizontal Display Width Register RW

    263
  • REG[05h] Horizontal Non-Display Period Register RW

    263
  • REG[06h] HRTC/FPLINE Start Position Register RW

    263
  • REG[07h] HRTC/FPLINE Pulse Width Register RW

    263
  • REG[08h] Vertical Display Height Register 0 RW

    263
  • REG[09h] Vertical Display Height Register 1 RW

    263
  • REG[0Ah] Vertical Non-Display Period Register RW

    263
  • REG[0Bh] VRTC/FPFRAME Start Position Register RW

    263
  • REG[0Ch] VRTC/FPFRAME Pulse Width Register RW

    263
  • REG[0Dh] Display Mode Register RW

    263
  • REG[0Eh] Screen 1 Line Compare Register 0 RW

    263
  • REG[0Fh] Screen 1 Line Compare Register 1 RW

    263
  • REG[10h] Screen 1 Display Start Address Register 0 RW

    263
  • REG[11h] Screen 1 Display Start Address Register 1 RW

    263
  • REG[12h] Screen 1 Display Start Address Register 2 RW

    263
  • REG[13h] Screen 2 Display Start Address Register 0 RW

    263
  • REG[14h] Screen 2 Display Start Address Register 1 RW

    263
  • REG[15h] Screen 2 Display Start Address Register 2 RW

    263
  • REG[16h] Memory Address Offset Register 0 RW

    263
  • REG[17h] Memory Address Offset Register 1 RW

    263
  • REG[18h] Pixel Panning Register RW

    263
  • REG[19h] Clock Configuration Register RW

    263
  • REG[1Ah] Power Save Configuration Register RW

    263
  • REG[1Bh] Miscellanious Register RW

    263
  • REG[1Ch] MD Configuration Readback Register 0 RO

    263
  • REG[1Dh] MD Configuration Readback Register 1 RO

    263
  • REG[1Eh] General IO Pins Configuration Register 0 RW

    263
  • REG[1Fh] General IO Pins Configuration Register 1 RW

    263
  • REG[20h] General IO Pins Control Register 0 RW

    263
  • REG[21h] General IO Pins Control Register 1 RW

    263
  • REG[22h] Performance Enhancement Register 0 RW

    263
  • REG[23h] Performance Enhancement Register 1 RW

    263
  • REG[24h] Look-Up Table Address Register RW

    263
  • REG[26h] Look-Up Table Data Register RW

    263
  • REG[27h] Ink/Cursor Control Register RW

    263
  • REG[28h] Cursor X Position Register 0 RW

    263
  • REG[29h] Cursor X Position Register 1 RW

    263
  • REG[2Ah] Cursor Y Position Register 0 RW

    263
  • REG[2Bh] Cursor Y Position Register 1 RW

    263
  • REG[2Ch] Ink/Cursor Color 0 Register 0 RW

    263
  • REG[2Dh] Ink/Cursor Color 0 Register 1 RW

    263
  • REG[2Eh] Ink/Cursor Color 1 Register 0 RW

    263
  • REG[2Fh] Ink/Cursor Color 1 Register 1 RW

    263
  • REG[30h] Ink/Cursor Start Address Select Register RW

    263
  • REG[31h] Alternate FRM Register RW

    263
• 13505CFG Configuration Program

  265
  • Table of Contents

    267
  • 13505CFG

    269
    • S1D13505 Supported Evaluation Platforms

      269
    • Installation

      270
    • Usage

      270
    • 13505CFG Configuration Tabs

      271
      • General Tab

        271
      • Preferences Tab

        273
      • Memory Tab

        274
      • Clocks Tab

        276
      • Panel Tab

        279
      • CRT/TV Tab

        283
      • Registers Tab

        284
    • 13505CFG Menus

      285
      • Open...

        285
      • Save

        286
      • Save As...

        286
      • Configure Multiple

        287
      • Export

        288
      • Enable Tooltips

        289
      • ERD on the Web

        289
      • About 13505CFG

        289
    • Comments

      289
• 13505SHOW Demonstration Program

  291
  • 13505SHOW

    293
    • S1D13505 Supported Evaluation Platforms

      293
    • Installation

      293
    • Usage

      294
    • 13505SHOW Examples

      294
      • Using 13505SHOW For Demonstration

        294
      • Using 13505SHOW For Testing

        295
    • Comments

      296
    • Program Messages

      297
• 13505SPLT Display Utility

  299
  • 13505SPLT

    301
    • S1D13505 Supported Evaluation Platforms

      301
    • Installation

      301
    • Usage

      302
    • 13505SPLT Example

      302
    • Comments

      302
    • Program Messages

      303
• 13505VIRT Display Utility

  305
  • 13505VIRT

    307
    • S1D13505 Supported Evaluation Platforms

      307
    • Installation

      307
    • Usage

      308
    • 13505VIRT Example

      309
    • Comments

      309
    • Program Messages

      309
• 13505PLAY Diagnostic Utility

  311
  • 13505PLAY

    313
    • S1D13505 Supported Evaluation Platforms

      313
    • Installation

      313
    • Usage

      314
    • 13505PLAY Example

      315
    • Scripting

      316
    • Comments

      316
    • Program Messages

      317
• 13505BMP Demonstration Program

  319
  • 13505BMP

    321
    • S1D13505 Supported Evaluation Platforms

      321
    • Installation

      321
    • Usage

      321
    • Hardware Cursor/Ink Layer

      322
    • 13505BMP Examples

      323
    • Comments

      323
    • Program Messages

      324
• 13505PWR Software Suspend Power Sequencing Utility

  327
  • 13505PWR

    329
    • S1D13505 Supported Evaluation Platforms

      329
    • Installation

      329
    • Usage

      330
    • 13505PWR Examples

      330
    • Comments

      331
    • Program Messages

      331
• Windows® CE 2.x Display Drivers

  333
  • WINDOWS® CE 2.x DISPLAY DRIVERS

    335
    • Example Driver Builds

      336
    • Installation for CEPC Environment

      342
    • Configuration

      343
      • Compile Switches

        343
      • Mode File

        344
    • Comments

      345
• Wind River WindML v2.0 Display Drivers

  347
  • Wind River WindML v2.0 DISPLAY DRIVERS

    349
    • Building a WindML v2.0 Display Driver

      350
      • 1. Create a working directory and unzip the WindML display driver into it.

        350
      • 2. Configure for the target execution model.

        350
      • 3. Build a boot ROM image.

        350
      • 4. Create a bootable disk (in drive A:).

        350
      • 5. If necessary, generate a new mode0.h configuration file.

        350
      • 6. Build the WindML v2.0 library.

        351
      • 7. Open the S1D13505 workspace.

        351
      • 8. Add support for single line comments.

        351
        • a. In the Tornado “Workspace Views” window, click on the “Builds” tab.

          351
        • b. Expand the “8bpp Builds” (or “16bpp Builds”) view by clicking on the “+” next to it. The expan...

          351
        • c. Select the “C/C++ compiler” tab to display the command switches used in the build. Remove the ...

          351
      • 9. Compile the VxWorks image.

        351
      • 10. Copy the VxWorks file to the diskette.

        351
      • 11. Start the VxWorks demo.

        351
• Wind River UGL v1.2 Display Drivers

  353
  • Wind River UGL v1.2 Display Drivers

    355
    • Building a UGL v1.2 Display Driver

      356
      • 1. Create a working directory and unzip the UGL display driver into it.

        356
      • 2. Configure for the target execution model.

        356
      • 3. Build a boot ROM image.

        356
      • 4. Create a bootable disk (in drive A:).

        356
      • 5. If necessary, generate a new mode0.h configuration file.

        356
      • 6. Open the S1D13505 workspace.

        357
      • 7. Add support for single line comments.

        357
        • a. In the Tornado “Workspace” window, click on the “Builds” tab.

          357
        • b. Expand the “8bpp Builds” (or “16bpp Builds”) view by clicking on the “+” next to it. The expan...

          357
        • c. Select the “C/C++ compiler” tab to display the command switches used in the build. Remove the ...

          357
      • 8. Compile the VxWorks image.

        357
      • 9. Copy the VxWorks file to the diskette.

        357
      • 10. Start the VxWorks demo.

        357
• Windows® CE 3.x Display Drivers

  359
  • WINDOWS® CE 3.x DISPLAY DRIVERS

    361
    • Example Driver Builds

      362
    • Installation for CEPC Environment

      368
    • Configuration

      369
      • Compile Switches

        369
      • Mode File

        370
      • Resource Management Issues

        371
    • Comments

      374
• SDU1355B0C Rev. 1.0 ISA Bus Evaluation Board User Manual

  375
  • Table of Contents

    377
  • List of Tables

    379
  • List of Figures

    379
  • 1 Introduction

    381
    • 1.1 Features

      381
  • 2 Installation and Configuration

    382
    • Table 21: Configuration DIP Switch Settings

      382
    • Table 22: Host Bus Selection

      382
    • Table 23: Jumper Settings

      382
  • 3 LCD Interface Pin Mapping

    383
    • Table 31: LCD Signal Connector (J6)

      383
  • 4 CPU/Bus Interface Connector Pinouts

    384
    • Table 41: CPU/BUS Connector (H1) Pinout

      384
    • Table 42: CPU/BUS Connector (H2) Pinout

      385
  • 5 Host Bus Interface Pin Mapping

    386
    • Table 51: CPU Interface Pin Mapping

      386
  • 6 Technical Description

    387
    • 6.1 ISA Bus Support

      387
    • 6.2 Non-ISA Bus Support

      387
    • 6.3 DRAM Support

      389
    • 6.4 Decode Logic

      389
    • 6.5 Clock Input Support

      389
    • 6.6 Monochrome LCD Panel Support

      389
    • 6.7 Color Passive LCD Panel Support

      389
    • 6.8 Color TFT/D-TFD LCD Panel Support

      390
    • 6.9 CRT Support

      390
    • 6.10 Power Save Modes

      390
    • 6.11 Adjustable LCD Panel Negative Power Supply

      390
    • 6.12 Adjustable LCD Panel Positive Power Supply

      390
    • 6.13 CPU/Bus Interface Header Strips

      391
    • 6.14 Schematic Notes

      391
  • 7 Parts List

    392
  • 8 Schematic Diagrams

    394
    • Figure 1: S1D13505B00C Schematic Diagram (1 of 4)

      394
    • Figure 2: S1D13505B00C Schematic Diagram (2 of 4)

      395
    • Figure 3: S1D13505B00C Schematic Diagram (3 of 4)

      396
    • Figure 4: S1D13505B00C Schematic Diagram (4 of 4)

      397
• Evaluation Board User Manual

  399
  • Table of Contents

    401
  • List of Tables

    403
  • List of Figures

    403
  • 1 Introduction

    405
    • Reference

      405
  • 2 Features

    406
    • 2.1 S1D13505 Embedded RAMDAC LCD/CRT Controller

      406
      • 2.1.1 Display Buffer

        406
      • 2.1.2 LCD Display Support

        407
        • Table 21: LCD Connector Pinout

          408
      • 2.1.3 Touchscreen Support

        409
        • Table 22: Touchscreen Header (TS1) Pinout

          409
      • 2.1.4 CRT Support

        409
      • 2.1.5 Jumper Selection

        409
        • Table 23: Touchscreen Header Pinout

          409
      • 2.1.6 Adjustable LCD BIAS Power Supply

        409
  • 3 D9000 Specifics

    411
    • 3.1 Interface Signals

      411
      • 3.1.1 Connector Pinout for Channel A6 and A7

        411
        • Table 31: Connectors Pinout for Channel A7 

          411
        • Table 32: Connectors Pinout for Channel A6 

          413
      • 3.1.2 Memory Address (CS#, M/R#) Decoding

        415
    • 3.2 FPGA Code Functionality

      415
    • 3.3 Board Dimensions

      415
  • 4 Parts List

    416
  • 5 Schematic Diagrams

    417
    • Figure 51: S5U13505-D9000 Schematic Diagram (1 of 3)

      417
    • Figure 52: S5U13505-D9000 Schematic Diagram (2 of 3)

      418
    • Figure 53: S5U13505-D9000 Schematic Diagram (3 of 3)

      419
  • 6 Component Placement

    420
    • Figure 61: Component Placement

      420
• Power Consumption

  421
  • 1 S1D13505 Power Consumption

    423
    • 1.1 Conditions

      424
      • Table 11: S1D13505 Total Power Consumption

        424
  • 2 Summary

    424
• Interfacing to the Philips MIPS PR31500/PR31700 Processor

  425
  • Table of Contents

    427
  • List of Tables

    429
  • List of Figures

    429
  • 1 Introduction

    431
  • 2 Interfacing to the PR31500/PR31700

    432
  • 3 S1D13505 Host Bus Interface

    433
    • 3.1 PR31500/PR31700 Host Bus Interface Pin Mapping

      433
      • Table 31: PR31500/PR31700 Host Bus Interface Pin Mapping

        433
    • 3.2 PR31500/PR31700 Host Bus Interface Signals

      434
  • 4 Direct Connection to the Philips PR31500/PR31700

    435
    • 4.1 Hardware Description

      435
      • Figure 41: Typical Implementation of Direct Connection

        435
    • 4.2 S1D13505 Configuration

      436
      • Table 41: S1D13505 Configuration for Direct Connection

        436
    • 4.3 Memory Mapping and Aliasing

      437
      • Table 42: PR31500/PR31700 to PC Card Slots Address Remapping for Direct Connection

        437
  • 5 System Design Using the IT8368E PC Card Buffer

    438
    • 5.1 Hardware Description

      438
      • Figure 51: IT8368E Implementation Block Diagram

        438
    • 5.2 IT8368E Configuration

      439
    • 5.3 S1D13505 Configuration

      439
  • 6 Software

    440
  • 7 References

    441
    • 7.1 Documents

      441
    • 7.2 Document Sources

      441
  • 8 Technical Support

    442
    • 8.1 EPSON LCD/CRT Controllers (S1D13505)

      442
    • 8.2 Philips MIPS PR31500/PR31700 Processor

      442
    • 8.3 ITE IT8368E

      442
• Interfacing to the PC Card Bus

  443
  • Table of Contents

    445
  • List of Tables

    447
  • List of Figures

    447
  • 1 Introduction

    449
  • 2 Interfacing to the PC Card Bus

    450
    • 2.1 The PC Card System Bus

      450
      • 2.1.1 PC Card Overview

        450
      • 2.1.2 Memory Access Cycles

        450
        • Figure 21: PC Card Read Cycle

          451
        • Figure 22: PC Card Write Cycle

          452
  • 3 S1D13505 Host Bus Interface

    453
    • 3.1 PC Card Host Bus Interface Pin Mapping

      453
      • Table 31: PC Card Host Bus Interface Pin Mapping

        453
    • 3.2 PC Card Host Bus Interface Signals

      454
  • 4 PC Card to S1D13505 Interface

    455
    • 4.1 Hardware Description

      455
      • Figure 41: Typical Implementation of PC Card to S1D13505 Interface

        456
    • 4.2 S1D13505 Hardware Configuration

      457
      • Table 41: Summary of Power-On/Reset Options

        457
    • 4.3 Performance

      457
    • 4.4 Register/Memory Mapping

      458
      • Table 42: Register/Memory Mapping for Typical Implementation

        458
  • 5 Software

    459
  • 6 References

    460
    • 6.1 Documents

      460
    • 6.2 Document Sources

      460
  • 7 Technical Support

    461
    • 7.1 Epson LCD/CRT Controllers (S1D13505)

      461
    • 7.2 PC Card Standard

      461
• Interfacing to the NEC VR4102/VR4111™ Microprocessors

  463
  • Table of Contents

    465
  • List of Tables

    467
  • List of Figures

    467
  • 1 Introduction

    469
  • 2 Interfacing to the VR4102/VR4111

    470
    • 2.1 The NEC VR4102/VR4111 System Bus

      470
      • 2.1.1 Overview

        470
      • 2.1.2 LCD Memory Access Cycles

        471
        • Figure 21: NEC VR4102/VR4111 Read/Write Cycles

          471
  • 3 S1D13505 Host Bus Interface

    472
    • 3.1 Host Bus Interface Pin Mapping

      472
      • Table 31: Host Bus Interface Pin Mapping

        472
    • 3.2 Host Bus Interface Signals Descriptions

      473
  • 4 VR4102/VR4111 to S1D13505 Interface

    474
    • 4.1 Hardware Description

      474
      • Figure 41: NEC VR4102/VR4111 to S1D13505 Configuration Schematic

        474
    • 4.2 S1D13505 Hardware Configuration

      475
      • Table 41: Summary of Power-On/Reset Options

        475
    • 4.3 NEC VR4102/VR4111 Configuration

      475
  • 5 Software

    476
  • 6 References

    477
    • 6.1 Documents

      477
    • 6.2 Document Sources

      477
  • 7 Technical Support

    478
    • 7.1 EPSON LCD/CRT Controllers (S1D13505)

      478
    • 7.2 NEC Electronics Inc. (VR4102/VR4111).

      478
• Interfacing to the Motorola MPC821 Microprocessor

  479
  • Table of Contents

    481
  • List of Tables

    483
  • List of Figures

    483
  • 1 Introduction

    485
  • 2 Interfacing to the MPC821

    486
    • 2.1 The MPC8xx System Bus

      486
    • 2.2 MPC821 Bus Overview

      486
      • 2.2.1 Normal (Non-Burst) Bus Transactions

        487
        • Figure 21: Power PC Memory Read Cycle

          487
        • Figure 22: Power PC Memory Write Cycle

          488
      • 2.2.2 Burst Cycles

        488
    • 2.3 Memory Controller Module

      489
      • 2.3.1 General-Purpose Chip Select Module (GPCM)

        489
      • 2.3.2 User-Programmable Machine (UPM)

        490
  • 3 S1D13505 Host Bus Interface

    491
    • 3.1 PowerPC Host Bus Interface Pin Mapping

      491
      • Table 31: PowerPC Host Bus Interface Pin Mapping

        491
    • 3.2 PowerPC Host Bus Interface Signals

      492
  • 4 MPC821 to S1D13505 Interface

    493
    • 4.1 Hardware Description

      493
      • Figure 41: Typical Implementation of MPC821 to S1D13505 Interface

        493
    • 4.2 Hardware Connections

      494
      • Table 41: List of Connections from MPC821ADS to S1D13505 

        494
    • 4.3 S1D13505 Hardware Configuration

      496
      • Table 42: Summary of Power-On/Reset Options

        496
    • 4.4 Register/Memory Mapping

      496
    • 4.5 MPC821 Chip Select Configuration

      497
    • 4.6 Test Software

      498
  • 5 Software

    499
  • 6 References

    500
    • 6.1 Documents

      500
    • 6.2 Document Sources

      500
  • 7 Technical Support

    501
    • 7.1 EPSON LCD/CRT Controllers (S1D13505)

      501
    • 7.2 Motorola MPC821 Processor

      501
• Interfacing to the Toshiba MIPS TX3912 Processor

  503
  • Table of Contents

    505
  • List of Tables

    507
  • List of Figures

    507
  • 1 Introduction

    509
  • 2 Interfacing to the TX3912

    510
  • 3 S1D13505 Host Bus Interface

    511
    • 3.1 TX3912 Host Bus Interface Pin Mapping

      511
      • Table 31: TX3912 Host Bus Interface Pin Mapping

        511
    • 3.2 TX3912 Host Bus Interface Signals

      512
  • 4 Direct Connection to the Toshiba TX3912

    513
    • 4.1 Hardware Description

      513
      • Figure 41: Typical Implementation of Direct Connection

        513
    • 4.2 S1D13505 Configuration

      514
      • Table 41: S1D13505 Configuration for Direct Connection

        514
    • 4.3 Memory Mapping and Aliasing

      515
      • Table 42: TX3912 to PC Card Slots Address Remapping for Direct Connection

        515
  • 5 System Design Using the IT8368E PC Card Buffer

    516
    • 5.1 Hardware Description

      516
      • Figure 51: IT8368E Implementation Block Diagram

        516
    • 5.2 IT8368E Configuration

      517
    • 5.3 S1D13505 Configuration

      517
  • 6 Software

    518
  • 7 References

    519
    • 7.1 Documents

      519
    • 7.2 Document Sources

      519
  • 8 Technical Support

    520
    • 8.1 EPSON LCD/CRT Controllers (S1D13505)

      520
    • 8.2 Toshiba MIPS TX3912 Processor

      520
    • 8.3 ITE IT8368E

      520
• Interfacing to the NEC VR4121™ Microprocessor

  521
  • Table of Contents

    523
  • List of Tables

    525
  • List of Figures

    525
  • 1 Introduction

    527
  • 2 Interfacing to the NEC VR4121

    528
    • 2.1 The NEC VR4121 System Bus

      528
      • 2.1.1 Overview

        528
      • 2.1.2 LCD Memory Access Cycles

        529
        • Figure 21: NEC VR4121 Read/Write Cycles

          529
  • 3 S1D13505 Host Bus Interface

    530
    • 3.1 Host Bus Interface Pin Mapping

      530
      • Table 31: Host Bus Interface Pin Mapping

        530
    • 3.2 Host Bus Interface Signal Descriptions

      531
  • 4 VR4121 to S1D13505 Interface

    532
    • 4.1 Hardware Description

      532
      • Figure 41: NEC VR4121 to S1D13505 Configuration Schematic

        532
    • 4.2 S1D13505 Configuration

      533
      • Table 41: Summary of Power-On-Reset Options

        533
    • 4.3 NEC VR4121 Configuration

      533
    • 4.4 Memory Mapping and Aliasing

      534
  • 5 Software

    535
  • 6 References

    536
    • 6.1 Documents

      536
    • 6.2 Document Sources

      536
  • 7 Technical Support

    537
    • 7.1 Epson LCD/CRT Controllers (S1D13505)

      537
    • 7.2 NEC Electronics Inc. (VR4121).

      537
• Interfacing to the NEC V832™ Microprocessor

  539
  • Table of Contents

    541
  • List of Tables

    543
  • List of Figures

    543
  • 1 Introduction

    545
  • 2 Interfacing to the NEC V832

    546
    • 2.1 The NEC V832 System Bus

      546
      • 2.1.1 Overview

        546
      • 2.1.2 Access Cycles

        547
        • Figure 21: NEC V832 Read/Write Cycles

          547
  • 3 S1D13505 Host Bus Interface

    548
    • 3.1 Host Bus Interface Pin Mapping

      548
      • Table 31: Host Bus Interface Pin Mapping

        548
    • 3.2 Host Bus Interface Signal Descriptions

      549
  • 4 V832 to S1D13505 Interface

    550
    • 4.1 Hardware Description

      550
      • Figure 41: NEC V832 to S1D13505 Configuration Schematic

        550
    • 4.2 S1D13505 Hardware Configuration

      551
      • Table 41: Summary of Power-On/Reset Options

        551
    • 4.3 NEC V832 Configuration

      552
      • Table 42: NEC V832 Wait States vs. Bus Clock Frequency

        552
    • 4.4 Memory Mapping and Aliasing

      553
      • Table 43: NEC V832 IO Address Range For Each CSn Line

        553
  • 5 Software

    554
  • 6 References

    555
    • 6.1 Documents

      555
    • 6.2 Document Sources

      555
  • 7 Technical Support

    556
    • 7.1 Epson LCD/CRT Controllers (S1D13505)

      556
    • 7.2 NEC Electronics Inc. (V832).

      556