Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

1028

Datasheet

Input Status 0

Default: 00h

3

0b

RO

0 = VSYNC inactive (Indicates that a vertical retrace 

interval is not taking place). 

1 = VSYNC active (Indicates that a vertical retrace interval is taking place). 

Note:  

VGA pixel generation is not locked to the display output but is loosely coupled. A VSYNC 

indication may not occur during the actual VSYNC going to the display but during the 

VSYNC that is generated as part of the VGA pixel generation. The exact relationship will 

vary with the VGA display operational mode. This status bit will remain active when the 

VGA is disabled and the device is running in high resolution modes (non-VGA) to allow 

for applications that (now it is incorrect) use these status registers bits. In this case, the 

status will come from the pipe that the VGA is assigned to. 

Bits 4 and 5 of the Vertical Retrace End Register (CR11) previously could program this 

bit to generate an interrupt at the start of the vertical retrace interval. This ability to 

generate interrupts at the start of the vertical retrace interval is a feature that is largely 

unused by legacy software. Interrupts are not supported through the VGA register bits.

2:1

0b

RO

Read as 0s.

0

0b

RO

Display Enable is a status bit (bit 0) in VGA Input 

Status Register 1 that indicates when either a horizontal retrace interval or a vertical 

retrace interval is taking place. This was used with the IBM* EGA graphics system (and 

the ones that preceded it, including MDA and CGA). In those cases, it was important to 

check the status of this bit to ensure that one or the other retrace intervals was taking 

place before reading from or writing to the frame buffer. In these earlier systems, 

reading from or writing to frame buffer at times outside the retrace intervals meant that 

the CRT controller would be denied access to the frame buffer. This resulted in either 

snow or a flickering display. This bit provides compatibility with software designed for 

those early graphics controllers. This bit is currently used in DOS applications that 

access the palette to prevent the sparkle associated with read and write accesses to the 

palette ram with the same address on the same clock cycle. 

This status bit will remain active when the VGA display is disabled and the device is 

running in high resolution modes (non-VGA) to allow for applications that (now 

considered incorrect) use these status registers bits. In this case, the status will come 

from the pipe that the VGA is assigned to. When in panel fitting VGA or centered VGA 

operation, the meaning of these bits will not be consistent with native VGA timings. 

0 = Active display data is being sent to the display. Neither a horizontal retrace interval 

or a vertical retrace interval is currently taking place.  

1 = Either a horizontal retrace interval (horizontal blanking) or a vertical retrace interval 

(vertical blanking) is currently taking place.

Memory Mapped I/O Register

(Size: 8 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h