Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2131
18.6.18
XHC System Bus Configuration 2 (XHCC2)—Offset 44h
Access Method
18
0b
RW
XHC Initiated L1 Enable (XHCIL1E):
If set, allow the XHC initiated L1 power
mangement to be enabled.
Power Well:
Core
17
0b
RW
D3 Initiated L1 Enable (D3IL1E):
If set, allow PCI device state D3 initiated L1 power
managment to be enables. This bit can only be set if the XHCI L1 Override P2 chicken
bit is set.
Power Well:
Core
16:12
00h
RW
Periodic Complete Pre Wake Time (PCPWT):
signal . This allows for platform wake
time before the next scheduled periodic transaction. The value programmed in this field
represents the # of bytes consumed in the current micro-frame which is required to
allow for the periodic complete to de-assert. This allows for a programmable time to
cause the periodic complete to de-assert prior to the start of the next micro-frame.
Register Format: Bits (16:12) represnets the # of bytes remaining with a 256B
granularity. Periodic Complete will de-assert if the bytes consumed in the current micro-
frame is less
Power Well:
Core
11
0h
RW
SW Assisted xHC Idle (SWAXHCI):
This bit being set will indicate xHC idleness
(through SW means), which must be a '1' to allow L1 entry, and subsequently allow
backbone clock to be gated. This bit is to be set by Intel xHCI driver after checking that
the xHCI Controller will stay in idle state for a significant period of time, e.g. all ports
disconnected. This bit can be cleared under the following conditions (see SWAXHCI
Policy bits in xHC System Bus Configuration 2 register): n SW: SW could write 0 to clear
this bit. n HW: HW, under policy control, will clear this bit on an MMIO access to the Host
Controller. n HW: HW, under policy control, will clear this bit when HW exits Idle state.
Power Well:
Core
10:8
000b
RW
L23 to Host Reset Acknowledge Wait Count (L23HRAWC):
If programmed to non
zero, it allows a wait period after the L23 PHY has shutdown before returning host reset
acknowledge to PMC. 000: Disabled 001: 128 bb_cclk 010: 256 bb_cclk 011: 512
bb_cclk 100: 1024 bb_cclk 101: 2048 bb_cclk 110: 4096 bb_cclk 111: 131072 bb_cclk
Power Well:
Core
7:6
11b
RW
Upstream Type Arbiter Grant Count Posted (UTAGCP):
Grant count for IOSF
upstream L2 request type arbiter for posted type
Power Well:
Core
5:4
11b
RW
Upstream Type Arbiter Grant Count Non Posted (UDAGCNP):
Grant count for
IOSF upstream L2 type arbiter for non-posted type
Power Well:
Core
3:2
11b
RW
Upstream Type Arbiter Grant Count Completion (UDAGCCP) (UDAGCCP):
Grant
count for IOSF upstream L2 type arbiter for completion type
Power Well:
Core
1:0
01b
RW
Upstream Device Arbiter Grant Count (UDAGC) (UDAGC):
Grant count for IOSF
upstream L1 device arbiter
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description