Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2133

Default: 00000120h

13:12

00b

RW

Note: Irrespective of the setting of this 

field, SW write of 0 to SWAXHCI will clear the bit. 00b (default): xHC HW clears 

SWAXHCI bit upon: n MMIO access to Host Controller OR n xHC HW exits Idle state 01b: 

xHC HW does not autonomously clear SWAXHCI bit. The bit could be cleared only by 

SW. 10b: xHC HW clears SWAXHCI upon MMIO acces to Host Controller. xHC HW exit 

from Idle state will not clear SWAXHCI. 11b: Reserved

Core

11

0h

RW

This field controls delay on 

MMIO Read after MMIO Write. 0b (Default): Delay MMIO Read after MMIO Write 1b: Do 

not delay MMIO Read after MMIO Write Note that this delay applies after the second of 

the two DW writes in the case where the IOSF Gasket splits a QW write into two single 

DW writes to the IP.

Core

10

0h

RW

This field controls delay on 

MMIO Write after previous MMIO Write. 0b (Default): Do not delay MMIO Write after 

previous MMIO Write 1b: Delay MMIO Write after previous MMIO Write Note that the 

delay count does not apply on the second of the two DW writes that are generated by 

IOSF Gasket when it splits a QW write into two. In other words, the second of the two 

DW writes could happen without any delay with respect to the first DW write. This choice 

is being made for ease of ECO. The delay count, in this case, will apply after the second 

of the two DW writes.

Core

9:8

0h

RW

This field controls how the DMI L1 inhibit 

signal from USB3 to PMC will behave. 00: Never inhibit Cx 01: Inhibit Cx when 

Isochronous Endpoint is active (PPT Behavior) 10: Inhibit Cx when Periodic Active as 

defined in 40.4.3.2.1 11: Always inhibit Cx

Core

7:6

0h

RW

This field controls how the DMI L1 

inhibit signal from USB3 to DMI will behave. 00: Never inhibit DMI L1. 01: Inhibit DMI 

L1 when Isochronous Endpoint is active (PPT Behavior). 10: Inhibit DMI L1 when Priodic 

Active as defined in 40.4.3.2.1. 11: Inhibit DMI L1 if XHCC1.SWAXHCI = 0.

Core

5:3

0h

RW

If programmed to non zero, it 

allows L1 force P2 gating off the clock to be delayed after the time-out period specified. 

If wake up event is detected before the time-out, pclk remains alive and trigger L1 exit 

as though CPU host is causing the wake, 000: Disabled 001: 128 bb_cclk 010: 256 

bb_cclk 011: 512 bb_cclk 100: 1024 bb_cclk 101: 2048 bb_cclk 110: 4096 bb_cclk 

111: 131072 bb_cclk

Core

2:0

000b

RW

Read Request Size Control: This bit 

controls the maximum size of each Read Request. 000: 128B 001: 256B 010: 512B 011 

- 110: Reserved 111: 64B

Core

PCI Configuration Register

(Size: 32 bits)