Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2135
19:16
0h
RW
SS Backbone PXP Trunk Clock Gate Enable (SSTCGE):
This register determines the
SS Ux state(s) which will be exposed to Backbone PXP trunk gating of core clock. Uy is a
state allowed to result in trunk gating when ss_tcg_ux_en(x) is asserted. (0) ==) U0 or
deeper (1) ==) U1 or deeper (2) ==) U2 or deeper (3) ==) U3 or deeper
Power Well:
Core
15
0h
RW
XHC Ignore_EU3S (XHCIGEU3S):
This register determines if the xHC will use the
EU3S as a condition to allow for Frame timer gating. 0 - xHC may allow frame timer to
be gated when EU3S is set and all ports are in the required state. 1 - xHC may allow
frame timer to be gated regardless of EU3S.
Power Well:
Core
14
0h
RW
XHC Frame Timer Clock Shutdown Enable (XHCFTCLKSE):
This register
determines if the xHC will allow the frame timer clock to be gated. 0 - xHC will not allow
ICC PLL 96MHz output to be shutdown thus keeping the frame timer running. 1 - xHC
will allow ICC PLL 96MHz output to be shutdown under specific conditions.
Power Well:
Core
13
0h
RW
XHC Backbone PXP Trunk Clock Gate In Presence of ISOCH EP
(XHCBBTCGIPISO):
This register controls the policy on allowing Backbone PXP trunk
clock gate in the presence of IDLE ISOCH EP s with active DB. Allows the periodic active
to be used in enabling Backbone PXP trunk clock gating of core clock. 0 Trunk gate of
core clock is not allowed when ISOCH EP DB is set and ISOCH EP s are idle. 1 Allow
trunk gate of core clock when ISOCH EP DB is set and ISOCH EP s are idle.
Power Well:
Core
12
0h
RW
XHC HS Backbone PXP Trunk Clock Gate U2 non RWE (XHCHSTCGU2NRWE):
This register controls the policy on allowing Backbone PXP trunk gating of core clock
when there is atleast 1 non Remote Wake Enabled HS Port in U2. 0 Prevent trunk gate of
core clock when a non RWE HS Port is in U2. 1 Allow trunk gate of core clock when a non
RWE HS Port is in U2.
Power Well:
Core
11:10
0h
RW
XHC USB2 PLL Shutdown Lx Enable (XHCUSB2PLLSDLE):
This register determines
the HS Link state(s) which will be exposed to USB2 PLL Shutdown conditions on behalf
of all USB2 HS Ports. Ly is a state allowed to result in USB2 PLL Shutdown when en(x) is
asserted. (0) ==) L1 or deeper (1) ==) L2 or deeper
Power Well:
Core
9:8
01b
RW
HS Backbone PXP PLL Shutdown Ux Enable (HSUXDMIPLLSE):
This register
determines the Ux state(s) which will be exposed to PXP PLL Shutdown conditions. PLL
Shutdown is allowed in: 00b Disabled (Link states shall be disabled for DMI PLL
shutdown) 01b U0 or conditions for 10b setting. 10b U2 or conditions for 11b setting.
10b U3, Disconnected, Disabled or Powered-Off.
Power Well:
Core
7:5
001b
RW
SS Backbone PXP PLL Shutdown Ux Enable (SSPLLSUE):
This register determines
the Ux state(s) which will be exposed to DMI PLL Shutdown conditions. PLL Shutdown is
allowed in: 000b Disabled (Link states shall be ignored for DMI PLL shutdown). 001b U0
or conditions for 010b setting 010b U1 or conditions for 011b setting 011b U2 or
conditions for 100b setting 100b U3, Disconnected, Disabled or Powered-Off
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description