Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2137

Default: 30h

This feature is used to adjust any offset from the clock source that generates the clock 

that drives the SOF counter. When a new value is written into these six bits, the length 

of the frame is adjusted. Its initial programmed value is system dependent based on 

the accuracy of hardware USB clock and is initialized by system BIOS. This register 

should only be modified when the HChalted bit in the USBSTS register is a one. 

Changing value of this register while the host controller is operating yields undefined 

results.

Default: 20h

29:16

0000h

RO/V

The value in this 

register is updated in response to sample_now signal. Bits (29:16) reflect state of bits 

(13:0) of FRINDEX

Core

15:13

0h

RO

Reserved.

Core

12:0

0000h

RO/V

The value is updated in response to 

sample_now signal and provides information about offset within micro-frame. Captured 

value represents number of 8 high-speed bit time units from start of micro-frame. At 

the beginning of micro-frame captured value will be 0 and increase to maximum value 

at the end. Default maximum value is 7499 but it may be changed as result of 

adjustment done in FLA.

Core

PCI Configuration Register

(Size: 8 bits)

7

4

0

0

0

1

1

0

0

0

0

SBRN

7:0

30h

RO

A value of 30h indicates that this controller 

follows USB release 3.0.

SUS

PCI Configuration Register

(Size: 8 bits)