Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2136
Datasheet
18.6.20
Audio Time Synchronization (AUDSYNC)—Offset 58h
This 32 bit register is used for audio stream synchronization across different devices.
Global signal sample_now captures a value in AUDSYNC register.
Access Method
Default: 00000000h
4
0b
RW
XHC Backbone Local Clock Gating Enable (XHCBLCGE):
When set, this bit allows
XHCI Controller IP backbone clock to be locally gated when idle conditions are met.
Note: if XHC Dynamic Clock Gating Disable Fuse is '1', hardware will always see '0' as an
output from this register. BIOS reading this register should always return the correct
value.
Power Well:
Core
3
0b
RW
HS Link Trunk Clock Gating Enable (HSLTCGE):
When set, this bit allows High
Speed Link control's 480 MHz and its 48/60 MHz link clock trunk to be gated when idle
conditions are met. Note: if XHC Dynamic Clock Gating Disable Fuse is '1', hardware will
always see '0' as an output from this register. BIOS reading this register should always
return the correct value. BIOS need to query fuses to see if HW is enabled.
Power Well:
Core
2
0b
RW
SS Link Trunk Clock Gating Enable (SSLTCGE):
When set, this bit allows the
SuperSpeed Link control's 250 MHz and its divided 125 MHz link clock trunk to ge gated
when idle conditions are met. Note: if XHC Dynamic Clock Gating Disable Fuse is '1',
hardware will always see '0' as an output from this register. BIOS reading this register
should always return the correct value. BIOS need to query fuses to see if HW is
enabled.
Power Well:
Core
1
0b
RW
IOSF Backbone Trunk Clock Gating Enable (IOSFBTCGE):
When set, this bit allows
the IOSF backbone clock trunk to be gated when idle conditions are met.
Power Well:
Core
0
0b
RW
IOSF Gasket Backbone Local Clock Gating Enable (IOSFBLCGE):
When set, this
bit allows the IOSF Gasket backbone clock to be locally gated when idle conditions are
met. Note: if XHC Dynamic Clock Gating Disable Fuse is '1', hardware will always see '0'
as an output from this register. BIOS reading this register should always return the
correct value. BIOS need to query fuses to see if HW is enabled.
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rsvd
2
CMFI
Rsvd
1
CMFB
Bit
Range
Default &
Access
Field Name (ID): Description
31:30
0h
RO
Rsvd2:
Reserved.
Power Well:
Core