Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
2159
18.6.50
DFT 2 (DFT2)—Offset F4h
Not for EDS
Access Method
Default: 00000000h
6:3
0h
RW
Super Speed DFT CRC Select (SSDFTCRCSEL): 
Super Speed DFT CRC Select 
(SSDFTCRCSEL): These bits select which Super Speed DFT CRC value is reflected in 
SSDFTCRC bits. In addition, these bits also select which SuperSpeed DFT CRC MSB 
value is sent to GPIO monitor pin, i.e. sata3gp_gp37 to aid silicon debug. Live version of 
selected CRC's MSB will be sent to GPIO monitor pin, i.e. sata3gp_gp37. 0h (default): 
No SuperSpeed DFT CRC is selected. 1h: Data Payload CRC 2h: Link Management 
Packet CRC 3h: Transaction Packet CRC 4h: Isochronous Timestamp Packet CRC 5h: 
Data Packet Header CRC 6h: Link Command Packet CRC Others: Reserved
Power Well: 
Core
2:0
0h
RW
Super Speed DFT CRC Port Select (SSDFTCPS): 
One CRC per packet type is shared 
for all the Super Speed ports. These bits select the Super Speed port for which CRC data 
will be updated. 000b: (default) No SuperSpeed Port is selected 001b: Super Speed Port 
0 010b: Super Speed Port 1 011b: Super Speed Port 2 100b: Super Speed Port 3 101b: 
Super Speed Port 4 110b: Super Speed Port 5 Others: Reserved
Power Well: 
Core
Bit 
Range
Default & 
Access
Field Name (ID): Description
Type: 
PCI Configuration Register
(Size: 32 bits)
Offset: 
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TXCRC
UTMIDF
TP
S
UTMILPBKL
OOPN_3_0
UTMIOP
MOD
E
_1_0
UT
MI
T
E
R
M
SE
L
UTMIX
C
VRSE
LECT_1_0
UTMILPBKS
T
S
UTMILPBKEN
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:16
0000h
RO
TX CRC (TXCRC): 
These register bits contain the value of TX CRC. This TX CRC is 
placed right after the 480MHz XCLKQ.
Power Well: 
Core
15:12
0h
RW
UTMI+ DFT Port Select (UTMIDFTPS): 
One CRC is shared for all the UTMI+ ports. 
These bits select the UTMI+ port for which CRC data will be updated and loopback 
status reflected in UTMILPBKSTS. 0h: (default) No UTMI+ Port is selected 1h: UTMI+ 
Port 0 2h: UTMI+ Port 1 3h: UTMI+ Port 2 4h: UTMI+ Port 3 5h: UTMI+ Port 4 6h: 
UTMI+ Port 5 7h: UTMI+ Port 6 8h: UTMI+ Port 7 9h: UTMI+ Port 8 Ah: UTMI+ Port 9 
Bh: UTMI+ Port 10 Ch: UTMI+ Port 11 Dh: UTMI+ Port 12 Eh: UTMI+ Port 13 Others: 
Reserved
Power Well: 
Core