Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2186
Datasheet
Default: 00000000h
18.7.17
Configure (CONFIG)—Offset B8h
This register defines runtime xHC configuration parameters.
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DC
BAAP
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
00000000h
RW
Device Context Base Address Array Pointer (DCBAAP):
This field defines high
order bits of the 64-bit base address of the Device Context Pointer Array, which is a
table of address pointers that reference Device Context structures for the devices
attached to the host.
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rs
vd1
MaxSlotsE
n
Bit
Range
Default &
Access
Field Name (ID): Description
31:8
000000h
RO
Rsvd1:
Reserved.
Power Well:
Core
7:0
00h
RW
Max Device Slots Enabled (MaxSlotsEn):
This field specifies the maximum number
of enabled Device Slots. Valid values are in the range of 0 to MaxSlots. Enabled Devices
Slots are allocated contiguously, e.g. a value of 16 specifies that Device Slots 1 to 16 are
active. A value of '0' disables all Device Slots. A disabled Device Slot shall not respond
to Doorbell Register references.
This field shall not be modified by software if the xHC is running (Run/Stop (R/S) = '1').
Power Well:
Core