Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2188
Datasheet
18.7.19
Port 1 Power Management Status and Control USB2
(PORTPMSC1USB2)—Offset 484h
This register is in the Aux Power well. It is only reset by platform hardware during a
cold reset or in response to a Host Controller Reset (HCRST). The USB2 Port Power
Management Status and Control register provides the USB2 LPM parameters necessary
for the xHC to generate a LPM Token to the downstream device.
Access Method
19
0b
RW/C
Warm Port Reset Change (WRC):
Note: This register is sticky.
Power Well:
SUS
18
0b
RW/C
Port Enabled Disabled Change (PEC):
Note: This register is sticky.
Power Well:
SUS
17
0b
RW/C
Connect Status Change (CSC):
Note: This register is sticky.
Power Well:
SUS
16
0b
RW
Port Link State Write Strobe (LWS):
Reserved.
Power Well:
SUS
15:14
0h
RW
Port Indicator Control (PIC):
Note: This register is sticky.
Power Well:
SUS
13:10
0h
RW
Port Speed (Port_Speed):
Note: This register is sticky.
Power Well:
SUS
9
1b
RW
Port Power (PP):
Note: This register is sticky.
Power Well:
SUS
8:5
5h
RW
Port Link State (PLS):
Note: This register is sticky.
Power Well:
SUS
4
0b
RW/S
Port Reset (PR):
Reserved.
Power Well:
SUS
3
0b
RW
Over-current Active (OCA):
Note: This register is sticky.
Power Well:
SUS
2
0b
RO
Rsvd1:
Reserved.
Power Well:
Core
1
0b
RW/C
Port Enabled Disabled (PED):
Note: This register is sticky.
Power Well:
SUS
0
0b
RW
Current Connect Status (CCS):
Note: This register is sticky.
Power Well:
SUS
Bit
Range
Default &
Access
Field Name (ID): Description