Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2637

ADP Configuration Register

Default: 00000000h

ADP Control Register

2

0h

RO

Indicates the Device mode transceiver status. Indicates the Device mode 

transceiver status. The core updates this bit when OEVTEN.OTGBDevVBUSChngEvnt is 

set. 1b0: B-session is not valid 1b1: B-session is valid Note: This bit is applicable for 

OTG 2.0 and OTG 3.0 modes of operation.

1

0h

RO

Indicates the Host mode transceiver status. 1b0: A-session is not valid 1b1: 

A-session is valid

0

1h

RO

Connector ID Status: Indicates the connector ID status n 1'b0: The 

DWC_usb3 core is in A-device mode n 1'b1: The DWC_usb3 core isin B-device mode 

Note: The reset value of this field depends on the power-on value of the IDDIG signal 

from the PHY.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:22, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PrbP

er

Prb

D

el

ta

PrbDschg

RSVD0

31:30

0h

RW

Probe Period: These bits set the T_ADP_PRB as follows: n 2'b00: 0.775 sec n 

2'b01: 1.55 sec n 2'b10: 2.275 sec n 2'b11: Reserved The scaledown values for PrbPer 

are: n 2'b00: 12.5ms n 2'b01: 18.75ms n 2'b10: 25 ms n 2'b11: 31.25 ms

29:28

0h

RW

Probe Delta: These bits set the resolution for RTIM value. They are defined in 

units of 32 kHz clock cycles as follows: n2'b00: 1 cycles n 2'b01: 2 cycles n 2'b10: 3 

cycles n 2'b11: 4 cycles For example, if this value is chosen to be 2'b01, it means that 

RTIM increments for every two 32 kHz clock cycles.

27:26

0h

RW

Probe Discharge: These bits set the time for TADP_DSCHG. They are 

defined as follows: n 2'b00: 4 msec n 2'b01: 8 msec n 2'b10: 16 msec n 2'b11: 32 msec 

The scaledown values for the PrbDschg are as follows: n 2'b00: 62.5 us n 2'b01: 125 us 

n 2'b10: 250 us n 2'b11: 500 us

25:0

0h

RO

reserved