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Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
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Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
779
14.11.116 DPB_AUX_CH_CTL—Offset 64110h
Display Port B AUX Channel Control [DevCDV] AuxB control (dprrega_b0.v 
auxb_ctl_rdback)
Access Method
Default: 00050000h
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
GTTMMADR_LSB Type: 
PCI Configuration Register (Size: 32 
bits)
GTTMMADR_LSB Reference: 
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SE
ND
_B
US
Y
DONE
INT
E
RRUPT_ON_DONE
TIME
_
O
UT_ERRO
R
T
IM
E
_OUT_TIMER_V
ALUE
RECEIVE
_
ERRO
R
ME
S
SAG
E_S
IZ
E
PREC
HA
RGE
_
TIME
A
U
X_AK
SV_BU
FFER_S
E
LE
CT
INVE
R
T
_MANC
H
E
S
TE
R_TES
T
_MODE
SY
NC_O
NL
Y_C
LOC
K_RE
CO
VER
Y
_TES
T_MODE
DIS
A
BLE
_
DE_GLIT
C
H
_
TES
T
_MODE
DOU
B
LE
_PRECHARG
E
_TEST_MODE
_2X_BIT_CL
O
C
K
_DIVIDE
R
Bit 
Range
Default & 
Access
Field Name (ID): Description
31
0b
RW
SEND_BUSY: 
Setting this bit to a one initiates the transaction, when read this bit will 
be a 1 until the transmission completes. The transaction is completed when the 
response is received or when a timeout occurs. Do not write a 1 again until transaction 
completes. Writes of 0 will be ignored. 
30
0b
RW/1C
DONE: 
A sticky bit that indicates the transaction has completed. SW must write a 1 to 
this bit to clear the event.  
AccessType: One to Clear
29
0b
RW
INTERRUPT_ON_DONE: 
Enable an interrupt in the hotplug status register when the 
transaction completes or times out.
28
0b
RW/1C
TIME_OUT_ERROR: 
A sticky bit that indicates the transaction has timed out. SW must 
write a 1 to this bit to clear the event.  
AccessType: One to Clear
27:26
0b
RW
TIME_OUT_TIMER_VALUE: 
00: 400us (default) 
01: 600us 
10: 800us 
11: 1600us 
The time count depends on the 2X bit clock divider (bits 10:0) being programmed for 
2MHz.
25
0b
RW/1C
RECEIVE_ERROR: 
A sticky bit that indicates that the data received was corrupted, not 
in multiples of a full byte, or more than 20 bytes. SW must write a 1 to this bit to clear 
the event.  
AccessType: One to Clear