Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
780
Datasheet
14.11.117 DPB_AUX_CH_DATA1—Offset 64114h
Display Port B AUX Data Register 1 [DevCTG, DevCDV]
Access Method
Default: 00000000h
24:20
0b
RW
MESSAGE_SIZE:
This field is used to indicate the total number bytes to transmit
(including the header). It also indicates the number of bytes received in a transaction
(including the header). This field is valid only only when the done bit is set and timeout
or receive error has not occurred. Sync/Stop are not part of the message or the
message size.
Reads of this field will give the response message size.
The read value will not be valid while Busy bit 31 is asserted.
Message sizes of 0 or )20 are not allowed.
19:16
0101b
RW
PRECHARGE_TIME:
Used to determine the precharge time for the Aux Channel
drivers. The value is the number of microseconds times 2. This depends on the 2X bit
clock divider (bits 10:0) being programmed for 2MHz. Default is 5 decimal which gives
10us of precharge.
Example: For 12us precharge, program 6 (12us/2us).
15
0b
RW
AUX_AKSV_BUFFER_SELECT:
This bit selects whether some of the data to be written
over Display Port AUX comes from the Aksv buffer for HDCP authentication, or all from
the AUX Data registers.
Set this bit before initiating a transaction to write Aksv to the Display Port sink. All AUX
protocol must be followed and Message Size set to 9 bytes. The first DWord transmitted
will be from the AUX Data Register 1 for the header, then the DP_AUX_CH_AKSV_HI,
then the last byte from DP_AUX_CH_AKSV_LO. The sink response is read back as usual
from the AUX Data registers.
More than one AUX channel can select to use the Aksv buffer simultaneously.
0 (Default) Use AUX Data registers for regular data transmission
1 Use Aksv Buffer for part of the data transmission.
14
0b
RW
INVERT_MANCHESTER_TEST_MODE:
1 = Manchester code rising edge mid-clk
signifies one (test mode)
0 = Manchester code rising edge mid-clk signifies zero (default)
13
0b
RW
SYNC_ONLY_CLOCK_RECOVERY_TEST_MODE:
1 = Only recover clock during sync
pattern (test mode)
0 = Recover clock during sync pattern and data phase (default)
12
0b
RW
DISABLE_DE_GLITCH_TEST_MODE:
1 = Disable serial input de-glitch logic (test
mode)
0 = Enable serial input de-glitch logic (default)
11
0b
RW
DOUBLE_PRECHARGE_TEST_MODE:
1 = Precharge time is doubled
0 = Precharge time is as programmed
10:0
0b
RW
_2X_BIT_CLOCK_DIVIDER:
Used to determine the 2X bit clock the Aux Channel logic
runs on.
This value divides the input clock frequency down to 2X bit clock rate. The 2X bit clock
rate is ideally 2MHz (0.5us).
[DevCTG-A] the input clock is cdclk.
[DevCTG-B, DevCDV] the input clock is hrawclk (200MHz)
Example:
For 300MHz input clock and desired 2MHz 2X bit clock, program 150 (300MHz/2MHz).
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h