Fujitsu FR81S User Manual
CHAPTER 26: 16-BIT INPUT CAPTURE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : 16-BIT INPUT CAPTURE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
10
[bit8] IEI0: Effective edge indication bit
IEI0
Function
0
A falling edge is detected.
1
A rising edge is detected.
⋅
This effective edge indication bit for the capture register (IPCP) indicates that a rising or falling edge has
been detected.
⋅
When a falling edge is detected, this bit is set to "0".
⋅
When a rising edge is detected, this bit is set to "1".
⋅
This bit is read-only.
Note:
If EG01, EG00: bit1, bit0 of the input capture state control register (ICS) are set to 00B, the value read from
this register is meaningless.
[bit7] ICP1: Interrupt request flag bit
ICP1
Function
Read
Write
0
No effective edge is detected.
This bit is cleared.
1
An effective edge is detected.
This bit remains unaffected.
⋅
This bit is used as an interrupt request flag for the input capture.
⋅
This bit is immediately set to "1" when an effective edge from the external input pin is detected.
⋅
An interrupt is immediately generated when an effective edge is detected while the interrupt request enable
bit (ICE1: bit5) is set.
⋅
When this bit is set to "0":This bit is cleared.
⋅
When this bit is set to "1": This bit remains unaffected.
Notes:
⋅
If a read-modify-write (RMW) instruction is executed, "1" is always read.
⋅
If a software clear (write of "0") or a clear due to an interrupt clear signal ("H") and a hardware set
occur at the same time, the hardware set takes precedence.
[bit6] ICP0: Interrupt request flag bit
ICP0
Function
Read
Write
0
No effective edge is detected.
This bit is cleared.
1
An effective edge is detected.
This bit remains unaffected.
⋅
This bit is used as an interrupt request flag for the input capture.
⋅
This bit is immediately set to "1" when an effective edge from the external input pin is detected.
⋅
An interrupt is immediately generated when an effective edge is detected while the interrupt request enable
bit (ICE0: bit4) is set.
⋅
When this bit is set to "0":This bit is cleared.
⋅
When this bit is set to "1": This bit remains unaffected.
MB91520 Series
MN705-00010-1v0-E
999