Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
56
Write
TDR1n-0n(n=0 to 11) : Address Base addr + 04
H
(Access: Byte, Half-word,
Word)
31
30
29
28
27
26
25
24
bit
D31
D30
D29
D28
D27
D26
D25
D24
0
0
0
0
0
0
0
0
Initial value
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
Attribute
23
22
21
20
19
18
17
16
bit
D23
D22
D21
D20
D19
D18
D17
D16
1
1
1
1
1
1
1
1
Initial value
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
Attribute
15
14
13
12
11
10
9
8
bit
D15
D14
D13
D12
D11
D10
D9
D8
1
1
1
1
1
1
1
1
Initial value
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
Attribute
7
6
5
4
3
2
1
0
bit
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
1
Initial value
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
Attribute
The transmit data register (TDR) is the 32-bit data buffer register for sending serial data.
⋅
When transmit operations are enabled (SCR:TXE=1), if transmission data is written to the transmit data
register (TDR), the transmission data is transferred to the transmit shift register and converted to serial
data, then output from the serial data output pin (SOT Pin).
⋅
Depending on the data length, the transmitting data will be stored from the lower bit and other bits will
become “invalid”.
Example: When you transmit "45"h with 8 bits data length, D7-D0="45"h and D31-D8 will become
invalid.
⋅
Transmission data empty flag (SSR:TDRE) will be cleared to "0" when the transmission data is written
to the transmit data register (TDR).
⋅
The transmission data empty flag (SSR:TDRE) will be set to "1" once a transmission starts after the
transmission data has been transferred to the transmit shift register if the transmission FIFO is disabled or
empty.
⋅
You will be able to write transmission data when the transmission data empty flag (SSR:TDRE) is set to
"1". If the transmission interrupt is enabled, a transmission interrupt will occur. Writing next transmission
data should be performed after the generation of transmission interrupt or be done when the transmission
data empty flag (SSR:TDRE) is "1".
⋅
You will not be able to write transmission data when the transmission data empty flag (SSR:TDRE) is
"0" and transmission FIFO is disabled or full.
⋅
When you write to TDR, accesses must be made with following methods.
⋅
SSR:AWC=0: 16-bit access to lower 16 bits of TDR
⋅
SSR:AWC=1: 32-bit access
⋅
SSR:AWC=1 allows one-time write for any data length.
⋅
SSR:AWC=0 allows one-time write for any data length from 5 to 16 bits.
⋅
SSR:AWC=0 allows two-time writes for any data length with 20, 24, 32 bits.
When you select one of lower bits (SSR:ES=0), first write must be lower 16 bits of transmitting data and
second write must be upper 16 bits of transmitting data.
MB91520 Series
MN705-00010-1v0-E
1369