Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
305
Checksum is operated based on LIN data length setting bit (LAMCR:LDL3 to LDL0), and the normality
of the reception checksum is confirmed automatically. The arithmetic operations result of checksum can
be confirmed by LIN checksum error flag bit (LAMESR:LCSER). When LCSER is "1", the checksum
error is detected. At this time, when LIN checksum error interrupt enable bit (LAMIER:LCSERIE) is "1",
the interrupt is generated.
be confirmed by LIN checksum error flag bit (LAMESR:LCSER). When LCSER is "1", the checksum
error is detected. At this time, when LIN checksum error interrupt enable bit (LAMIER:LCSERIE) is "1",
the interrupt is generated.
When the checksum arithmetic operations is completed, the checksum arithmetic operations completion
flag bit (LAMSR:LCSC) becomes "1". At this time, when LIN checksum arithmetic operations
completion interrupt enable bit (LAMIER:LCSCIE) is "1", the interrupt is generated.
completion interrupt enable bit (LAMIER:LCSCIE) is "1", the interrupt is generated.
After the checksum reception is completed (LAMSR:LCSC=1), reception prohibition setting
(SCR:RXE=0) is done.
Figure 7-60 From ID Field reception to DATA Field reception (ID register use).
SSR : TDRE
Sync Field
SCR : RIE
ID Field
data
LAMCR : LAMEN
LAMCR : LIDEN
H : LIN assist mode processing enable
H : LIN ID register use enable
： Don’t care
checksum
Data １
Data N
LIN bus
6 7 SP ST 0 1 2 3 4 5 6 7 SP
ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3
0 1 2 3 4 5 6
SP ST 0 1 2 3 4 5 6 7 SP
ST 0 1 2 3 4 5 6 7
SP
7
ST
Data (N-1）
LAMSR : LAHC
LAMRID : LID5-0
ID Field value
SCR : TXE
L : transmission disable
SCR : TIE
L : transmission interrupt disable
SCR : RXE
SSR : RDRF
H : reception enable
H : reception interrupt enable
H : transmission data register empty
RDR
Data １
Data N
Data (N-1）
Data (N-2）
LAMCR : LDL3-0
Data length setting
L : reception disable
L : reception interrupt disable
Figure 7-61 From ID Field reception to DATA Field reception (ID register unused).
SSR : TDRE
Sync Field
SCR : RIE
ID Field
data
LAMCR : LAMEN
LAMCR : LIDEN
H : LIN assist mode processing enable
L : LIN ID register use disable
： Don’t care
checksum
Data １
Data N
LIN bus
6 7 SP ST 0 1 2 3 4 5 6 7 SP
ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3
0 1 2 3 4 5 6
SP ST 0 1 2 3 4 5 6 7 SP
ST 0 1 2 3 4 5 6 7
SP
7
ST
Data (N-1）
LAMSR : LAHC
LAMRID : LID5-0
SCR : TXE
L : transmission disable
SCR : TIE
L : transmission interrupt disable
SCR : RXE
SSR : RDRF
H : transmission data register empty
RDR
Data １
Data N
Data (N-1）
Data (N-2）
ID Field
LAMCR : LDL3-0
Data length setting
H : reception enable
H : reception interrupt enable
L : reception disable
L : reception interrupt disable
MB91520 Series
MN705-00010-1v0-E
1618