Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
367
When DMA mode is enable (SSR:DMA=1)
⋅
If the receive FIFO operation is disabled
(1) After sending an ACK signal, set the interrupt flag (IBCR:INT) to "1" to wait the I
2
C bus. You can
determine the interrupt occurrence due to slave address matching shown by IBCR:MSS bit, IBCR:ACT
bit and IBSR:FBT bit. Set the IBCR:ACKE bit to "1" and set the interrupt flag (IBCR: INT) to "0" to
release the I
2
C bus from the waiting state. See Table 8-9.
(2) Receive data full flag (SSR:RDRF) is set in "1" immediately after the reception 1 byte after the data of
one byte is received. The I
2
C bus is waited for IBCR:WSEL=1 immediately after the reception 1 byte
after the acknowledge is transmitted for IBCR:WSEL ="0" in the place where receive data full flag
(SSR:RDRF) is set in "1".
(3) The data received from the RDR register after the IBCR:ACKE bit is set clears receive data full flag
(SSR:RDRF) to "0" by reading and releases the I
2
C bus from the waiting state.
(4) Repeat Steps (2) and (3) until the stop condition or the repeated start condition is detected.
⋅
If the receive FIFO operation is enabled
(1) The interrupt flag (IBCR:INT) becomes "1" and waits for the I
2
C bus by detecting NACK. The I
2
C
bus is waited for when reception FIFO becomes full. The IBSR:SPC bit and the IBSR:RSC bit are
made "1" when the stop condition and the repetition start condition are detected and interrupt flag
(IBCR:INT) does not become "1" ( none waiting of the I
2
C bus). When a set value of the FBYTE
register is corresponding to the received number of data, reception FIFO makes the SSR:RDRF bit "1".
When the SMR:RIE bit is "1" at that time, the reception interrupt is generated.
(2) If the interrupt flag (IBCR:INT) is set to "1", the received data is read from the RDR register. After
reading all data sets, set the interrupt flag to "0" and release the I
2
C bus from the waiting state. If the
data received from the RDR register even once is read when reception FIFO becomes full, the I
2
C bus
is released from the waiting state. When the stop condition or the repeated start condition is detected, all
of the received data sets are read from the RDR register, and the IBSR:SPC bit or IBSR:RSC bit is
cleared to "0".
Figure 8-42 Slave Reception Interrupt (1)-when FIFO is Disabled
(SSR:DMA="0", IBCR:WSEL="0", IBSR:RSA="0")
S Slave Address W ACK Data ACK Data ACK Data NACK P or Sr
△ △ △ △▲
① ② ② ③
S: Start condition
W: Data direction bit (Write direction)
P: Stop condition
Sr: Repeated start condition
: Interrupt because of INTE = "1"
: Interrupt because of CNDE = "1"
(1) An interrupt generated by ACK output due to the match with the slave address
- Write ACKE="1", INT = "0"
(2) An interrupt generated by 1 byte reception + ACK response
- Read the reception data from the reception buffer, and write INT = "0"
(3) An interrupt generated by 1 byte reception + NACK response
- Read the reception data from the reception buffer, and then write INT = "0"
MB91520 Series
MN705-00010-1v0-E
1680