Manuali utente per STMicroelectronics M24C64-WBN6P Memory IC

Sommario

• 1 Description

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  • Figure 1. Logic diagram

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  • Table 1. Signal names

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  • Figure 2. 8-pin package connections, top view

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  • Figure 3. 5-bump WLCSP connections (top view)

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  • Figure 4. 8-bump thin WLCSP connections (top view)

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• 2 Signal description

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  • 2.1 Serial Clock (SCL)

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  • 2.2 Serial Data (SDA)

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  • 2.3 Chip Enable (E2, E1, E0)

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    • Figure 5. Device select code

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  • 2.4 Write Control (WC)

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  • 2.5 VSS (ground)

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  • 2.6 Supply voltage (VCC)

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    • 2.6.1 Operating supply voltage (VCC)

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    • 2.6.2 Power-up conditions

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    • 2.6.3 Device reset

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    • 2.6.4 Power-down conditions

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• 3 Memory organization

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  • Figure 6. Block diagram

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• 4 Device operation

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  • Figure 7. I2C bus protocol

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  • 4.1 Start condition

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  • 4.2 Stop condition

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  • 4.3 Data input

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  • 4.4 Acknowledge bit (ACK)

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  • 4.5 Device addressing

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    • Table 2. Device select code

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• 5 Instructions

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  • 5.1 Write operations

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    • Table 3. Most significant address byte

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    • Table 4. Least significant address byte

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    • 5.1.1 Byte Write

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      • Figure 8. Write mode sequences with WC = 0 (data write enabled)

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    • 5.1.2 Page Write

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      • Figure 9. Write mode sequences with WC = 1 (data write inhibited)

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    • 5.1.3 Write Identification Page (M24C64-D only)

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    • 5.1.4 Lock Identification Page (M24C64-D only)

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    • 5.1.5 ECC (Error Correction Code) and Write cycling

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    • 5.1.6 Minimizing Write delays by polling on ACK

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      • Figure 10. Write cycle polling flowchart using ACK

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  • 5.2 Read operations

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    • Figure 11. Read mode sequences

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    • 5.2.1 Random Address Read

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    • 5.2.2 Current Address Read

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    • 5.2.3 Sequential Read

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  • 5.3 Read Identification Page (M24C64-D only)

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  • 5.4 Read the lock status (M24C64-D only)

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• 6 Initial delivery state

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• 7 Maximum rating

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  • Table 5. Absolute maximum ratings

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• 8 DC and AC parameters

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  • Table 6. Operating conditions (voltage range W)

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  • Table 7. Operating conditions (voltage range R)

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  • Table 8. Operating conditions (voltage range F)

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  • Table 9. AC measurement conditions

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  • Figure 12. AC measurement I/O waveform

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  • Table 10. Input parameters

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  • Table 11. Cycling performance by groups of four bytes

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  • Table 12. Memory cell data retention

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  • Table 13. DC characteristics (M24C64-W, device grade 6)

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  • Table 14. DC characteristics (M24C64-R, device grade 6)

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  • Table 15. DC characteristics (M24C64-F, M24C64-DF, device grade 6)

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  • Table 16. 400 kHz AC characteristics

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  • Table 17. 1 MHz AC characteristics

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  • Figure 13. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz

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  • Figure 14. Maximum Rbus value versus bus parasitic capacitance Cbus) for an I2C bus at maximum frequency fC = 1MHz

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  • Figure 15. AC waveforms

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• 9 Package mechanical data

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  • Figure 16. TSSOP8 – 8-lead thin shrink small outline, package outline

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  • Table 18. TSSOP8 – 8-lead thin shrink small outline, package mechanical data

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  • Figure 17. SO8N – 8-lead plastic small outline, 150 mils body width, package outline

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  • Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package data

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  • Figure 18. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline

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  • Table 20. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data

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  • Figure 19. UFDFPN8 (MLP8) – package outline (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead)

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  • Table 21. UFDFPN8 (MLP8) – package dimensions (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead)

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  • Figure 20. WLCSP 5-bump wafer-length chip-scale package outline (M24C64-FCS6TP/K)

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  • Table 22. WLCSP 5-bump wafer-length chip-scale package mechanical data (M24C64-FCS6TP/K)

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  • Figure 21. Thin WLCSP 8-bump wafer-length chip-scale package outline (M24C64-DFCT6TP/K)

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  • Table 23. Thin WLCSP 8-bump wafer-length chip-scale package mechanical data (M24C64-DFCT6TP/K)

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• 10 Part numbering

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  • Table 24. Ordering information scheme

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• 11 Revision history

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  • Table 25. Document revision history

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