Texas Instruments Delfino C28346 DIM168 ControlCARD TMDSCNCD28346-168 사용자 매뉴얼

차례

• Table of Contents

  2
• 1  TMS320C2834x (Delfino) MCUs

  10
  • 1.1 Overview

    10
  • 1.2 Features

    10
  • 1.3 Getting Started

    11
• 2 Introduction

  12
  • 2.1 Pin Assignments

    15
  • 2.2 Signal Descriptions

    23
• 3 Functional Overview

  34
  • 3.1 Memory Maps

    35
  • 3.2 Brief Descriptions

    40
    • 3.2.1 C28x CPU

      40
    • 3.2.2 Memory Bus (Harvard Bus Architecture)

      40
    • 3.2.3 Peripheral Bus

      40
    • 3.2.4 Real-Time JTAG and Analysis

      41
    • 3.2.5 External Interface (XINTF)

      41
    • 3.2.6 M0, M1 SARAMs

      41
    • 3.2.7 L0, L1, L2, L3, L4, L5, L6, L7, H0, H1, H2, H3, H4, H5 SARAMs

      41
    • 3.2.8 Boot ROM

      42
    • 3.2.9 Security

      42
    • 3.2.10 Peripheral Interrupt Expansion (PIE) Block

      43
    • 3.2.11 External Interrupts (XINT1–XINT7, XNMI)

      43
    • 3.2.12 Oscillator and PLL

      43
    • 3.2.13 Watchdog

      43
    • 3.2.14 Peripheral Clocking

      43
    • 3.2.15 Low-Power Modes

      43
    • 3.2.16 Peripheral Frames 0, 1, 2, 3 (PFn)

      44
    • 3.2.17 General-Purpose Input/Output (GPIO) Multiplexer

      44
    • 3.2.18 32-Bit CPU-Timers (0, 1, 2)

      44
    • 3.2.19 Control Peripherals

      45
    • 3.2.20 Serial Port Peripherals

      45
  • 3.3 Register Map

    46
  • 3.4 Device Emulation Registers

    47
  • 3.5 Interrupts

    48
    • 3.5.1 External Interrupts

      52
  • 3.6 System Control

    53
    • 3.6.1 OSC and PLL Block

      54
      • 3.6.1.1 External Reference Oscillator Clock Option

        56
      • 3.6.1.2 PLL-Based Clock Module

        57
      • 3.6.1.3 Loss of Input Clock

        58
    • 3.6.2 Watchdog Block

      59
  • 3.7 Low-Power Modes Block

    60
• 4 Peripherals

  61
  • 4.1 DMA Overview

    61
  • 4.2 32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2

    63
  • 4.3 Enhanced PWM Modules

    65
  • 4.4 High-Resolution PWM (HRPWM)

    69
  • 4.5 Enhanced CAP Modules

    70
  • 4.6 Enhanced QEP Modules

    72
  • 4.7 External ADC Interface

    73
  • 4.8 Multichannel Buffered Serial Port (McBSP) Module

    75
  • 4.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)

    78
  • 4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)

    84
  • 4.11 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D)

    88
  • 4.12 Inter-Integrated Circuit (I2C)

    91
  • 4.13 GPIO MUX

    92
  • 4.14 External Interface (XINTF)

    99
• 5 Device Support

  101
  • 5.1 Device and Development Support Tool Nomenclature

    101
  • 5.2 Documentation Support

    103
  • 5.3 Community Resources

    106
• 6 Electrical Specifications

  107
  • 6.1 Absolute Maximum Ratings

    107
  • 6.2 Recommended Operating Conditions

    108
  • 6.3 Electrical Characteristics

    108
  • 6.4 Current Consumption

    109
    • 6.4.1 Reducing Current Consumption

      111
  • 6.5 Thermal Design Considerations

    113
  • 6.6 Emulator Connection Without Signal Buffering for the MCU

    113
  • 6.7 Timing Parameter Symbology

    114
    • 6.7.1 General Notes on Timing Parameters

      114
    • 6.7.2 Test Load Circuit

      114
    • 6.7.3 Device Clock Table

      115
  • 6.8 Clock Requirements and Characteristics

    117
  • 6.9 Power Sequencing

    118
    • 6.9.1 Power Management and Supervisory Circuit Solutions

      119
  • 6.10 General-Purpose Input/Output (GPIO)

    122
    • 6.10.1  GPIO - Output Timing

      122
    • 6.10.2  GPIO - Input Timing

      123
    • 6.10.3 Sampling Window Width for Input Signals

      124
    • 6.10.4 Low-Power Mode Wakeup Timing

      125
  • 6.11 Enhanced Control Peripherals

    128
    • 6.11.1 Enhanced Pulse Width Modulator (ePWM) Timing

      128
    • 6.11.2 Trip-Zone Input Timing

      128
    • 6.11.3 High-Resolution PWM Timing

      129
    • 6.11.4 Enhanced Capture (eCAP) Timing

      129
    • 6.11.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing

      130
    • 6.11.6 ADC Start-of-Conversion Timing

      131
  • 6.12 External Interrupt Timing

    131
  • 6.13 I2C Electrical Specification and Timing

    132
  • 6.14 Serial Peripheral Interface (SPI) Timing

    132
    • 6.14.1 Master Mode Timing

      132
    • 6.14.2 SPI Slave Mode Timing

      137
  • 6.15 External Interface (XINTF) Timing

    140
    • 6.15.1 USEREADY = 0

      140
    • 6.15.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)

      141
    • 6.15.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)

      142
    • 6.15.4 XINTF Signal Alignment to XCLKOUT

      144
    • 6.15.5 External Interface Read Timing

      145
    • 6.15.6 External Interface Write Timing

      147
    • 6.15.7 External Interface Ready-on-Read Timing With One External Wait State

      149
    • 6.15.8 External Interface Ready-on-Write Timing With One External Wait State

      152
    • 6.15.9  XHOLD and XHOLDA Timing

      155
  • 6.16 Multichannel Buffered Serial Port (McBSP) Timing

    157
    • 6.16.1 McBSP Transmit and Receive Timing

      157
    • 6.16.2 McBSP as SPI Master or Slave Timing

      160
• 7 Revision History

  164
• 8 Thermal and Mechanical Data

  165