사용자 설명서차례Table of Contents3Preface61 Introduction71.1 Purpose of the Peripheral71.2 Features71.3 Functional Block Diagram81.4 Supported Use Case Statement81.5 Industry Standard(s) Compliance Statement82 Peripheral Architecture92.1 Clock Control92.1.1 Clock Source92.1.2 Clock Configuration102.1.3 DDR2 Memory Controller Internal Clock Domains102.2 Memory Map102.3 Signal Descriptions112.4 Protocol Description(s)122.4.1 Refresh Mode132.4.2 Deactivation (DCAB and DEAC)142.4.3 Activation (ACTV)162.4.4 READ Command172.4.5 Write (WRT) Command182.4.6 Mode Register Set (MRS and EMRS)192.5 Memory Width and Byte Alignment202.6 Endianness Support212.7 Address Mapping222.8 DDR2 Memory Controller Interface262.8.1 Command Ordering and Scheduling, Advanced Concept272.8.2 Command Starvation282.8.3 Possible Race Condition282.9 Refresh Scheduling292.10 Self-Refresh Mode292.11 Reset Considerations302.12 VTP IO Buffer Calibration312.13 Auto-Initialization Sequence312.13.1 Initializing Configuration Registers322.13.2 Initializing Following Device Power Up and Device RESET332.14 Interrupt Support342.15 DMA Event Support342.16 Power Management342.16.1 DDR2 Memory Controller Clock Stop Procedure352.17 Emulation Considerations353 Supported Use Cases363.1 Connecting the DDR2 Memory Controller to DDR2 Memory363.2 Configuring Memory-Mapped Registers to Meet DDR2-400 Specification363.2.1 Configuring SDRAM Bank Configuration Register (SDBCR)383.2.2 Configuring SDRAM Refresh Control Register (SDRCR)383.2.3 Configuring SDRAM Timing Registers (SDTIMR and SDTIMR2)393.2.4 Configuring DDR PHY Control Register (DDRPHYCR)404 DDR2 Memory Controller Registers414.1 SDRAM Status Register (SDRSTAT)424.2 SDRAM Bank Configuration Register (SDBCR)434.3 SDRAM Refresh Control Register (SDRCR)454.4 SDRAM Timing Register (SDTIMR)464.5 SDRAM Timing Register 2 (SDTIMR2)474.6 Peripheral Bus Burst Priority Register (PBBPR)484.7 Interrupt Raw Register (IRR)494.8 Interrupt Masked Register (IMR)504.9 Interrupt Mask Set Register (IMSR)514.10 Interrupt Mask Clear Register (IMCR)524.11 DDR PHY Control Register (DDRPHYCR)534.12 VTP IO Control Register (VTPIOCR)544.13 DDR VTP Register (DDRVTPR)554.14 DDR VTP Enable Register (DDRVTPER)55Appendix A Revision History56크기: 454킬로바이트페이지: 57Language: English매뉴얼 열기